void pnp_sleep_wk(void *context)
{
_irqL irqL;
_adapter *padapter = (_adapter *)context;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv;
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("pnp_sleep_wk ===>\n"));
_enter_critical(&pmlmepriv->lock, &irqL );
if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
{
indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not
free_assoc_resources(padapter);
#ifndef CONFIG_POWER_DOWN_MODE
disassoc_cmd(padapter);
#endif
}
_exit_critical(&pmlmepriv->lock, &irqL );
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("pnp_sleep_wk:fwstate:%d\n", pmlmepriv->fw_state));
#ifdef CONFIG_POWER_DOWN_MODE
//before enter powerdown mode, we must ensure FW in S4 state.
if (padapter->pwrctrlpriv.pwr_mode > PS_MODE_ACTIVE) {
padapter->pwrctrlpriv.pwr_mode = PS_MODE_ACTIVE;
_enter_pwrlock(&(padapter->pwrctrlpriv.lock));
set_rpwm(padapter, PS_STATE_S4);
_exit_pwrlock(&(padapter->pwrctrlpriv.lock));
}
while (pwrctrl->cpwm != PS_STATE_S4) {
//waiting FW to become ACTIVE.
msleep_os(10);
}
#endif
write16(padapter, SDIO_HIMR, 0);
pwrctrl->pnp_bstop_trx = _TRUE;
padapter->hw_init_completed = _FALSE;
NdisMSetInformationComplete(padapter->hndis_adapter, NDIS_STATUS_SUCCESS);
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("pnp_sleep_wk <===\n"));
}
void pnp_sleep_wk(void *context)
{
_irqL irqL;
_adapter *padapter = (_adapter *)context;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv;
_enter_critical(&pmlmepriv->lock, &irqL );
if (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)
{
indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not
}
_exit_critical(&pmlmepriv->lock, &irqL );
RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("\npnp_sleep_wk:fwstate:%d\n", pmlmepriv->fw_state));
pwrctrl->pnp_bstop_trx=_TRUE;
//delay 1 second then cancel IRP
//msleep_os(1000);
//cancel irp
// 1. tx/rx irp
// 2.int irp
// 3.reg read/write irp
rtl871x_intf_stop(padapter);
msleep_os(1000);
//Turn off LDO
rtl871x_hal_deinit(padapter);
padapter->hw_init_completed = _FALSE;
NdisMSetInformationComplete(padapter->hndis_adapter, NDIS_STATUS_SUCCESS);
}
u8 usb_hal_bus_deinit(_adapter * padapter){
u8 tmp8;
_func_enter_;
//4 Turn off LDO
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_REGISTER, RT_USB_LDO, 0, &tmp8, 1, _TRUE);
DEBUG_ERR(("usb_hal_bus_deinit() : LDO = %d\n", tmp8));
if (tmp8 == 0x00){
DEBUG_ERR(("usb_hal_bus_deinit() : LDO is off. No necessary to Turn it off.\n"));
} else {
DEBUG_ERR(("usb_hal_bus_deinit() : LDO is on. Need to Turn it off.\n"));
usbvendorrequest(&padapter->dvobjpriv, RT_USB_SET_REGISTER, RT_USB_LDO, RT_USB_LDO_OFF, NULL, 0, _FALSE);
msleep_os(100);
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_REGISTER, RT_USB_LDO, 0, &tmp8, 1, _TRUE);
DEBUG_ERR(("usb_hal_bus_deinit() : LDO = %d\n", tmp8));
}
_func_exit_;
return _SUCCESS;
}
u8 usb_hal_bus_init(_adapter * padapter)
{
u8 val8 = 0;
u8 ret;
u8 PollingCnt = 20;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
ret =_SUCCESS;
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("chip_version=%d\n", pregistrypriv->chip_version));
//pregistrypriv->chip_version = RTL8712_2ndCUT;//RTL8712_1stCUT;
if(pregistrypriv->chip_version == RTL8712_FPGA)
{
val8 = 0x01;
write8(padapter, SYS_CLKR, val8);//switch to 80M clock
val8 = read8(padapter, SPS1_CTRL);
val8 = val8 |0x01;
write8(padapter, SPS1_CTRL, val8);//enable VSPS12 LDO Macro block
val8 = read8(padapter, AFE_MISC);
val8 = val8 |0x01;
write8(padapter, AFE_MISC, val8);//Enable AFE Macro Block's Bandgap
val8 = read8(padapter, LDOA15_CTRL);
val8 = val8 |0x01;
write8(padapter, LDOA15_CTRL, val8);//enable LDOA15 block
val8 = read8(padapter, SPS1_CTRL);
val8 = val8 |0x02;
write8(padapter, SPS1_CTRL, val8);//Enable VSPS12_SW Macro Block
val8 = read8(padapter, AFE_MISC);
val8 = val8 |0x02;
write8(padapter, AFE_MISC, val8);//Enable AFE Macro Block's Mbias
val8 = read8(padapter, SYS_ISO_CTRL+1);
val8 = val8 |0x08;
write8(padapter, SYS_ISO_CTRL+1, val8);//isolate PCIe Analog 1.2V to PCIe 3.3V and PCIE Digital
val8 = read8(padapter, SYS_ISO_CTRL+1);
val8 = val8 & 0xEF;
write8(padapter, SYS_ISO_CTRL+1, val8);//attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, AFE_XTAL_CTRL+1);
val8 = val8 & 0xFB;
write8(padapter, AFE_XTAL_CTRL+1, val8);//enable AFE clock
val8 = read8(padapter, AFE_PLL_CTRL);
val8 = val8 |0x01;
write8(padapter, AFE_PLL_CTRL, val8);//Enable AFE PLL Macro Block
val8 = 0xEE;
write8(padapter, SYS_ISO_CTRL, val8);//release isolation AFE PLL & MD
val8 = read8(padapter, SYS_CLKR+1);
val8 = val8 |0x08;
write8(padapter, SYS_CLKR+1, val8);//enable MAC clock
val8 = read8(padapter, SYS_FUNC_EN+1);
val8 = val8 |0x08;
write8(padapter, SYS_FUNC_EN+1, val8);//enable Core digital and enable IOREG R/W
val8 = val8 |0x80;
write8(padapter, SYS_FUNC_EN+1, val8);//enable REG_EN
val8 = read8(padapter, SYS_CLKR+1);
val8 = (val8 |0x80)&0xBF;
write8(padapter, SYS_CLKR + 1, val8);//switch the control path
val8 = 0xFC;
write8(padapter, CR, val8);
val8 = 0x37;
write8(padapter, CR+1, val8);
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
//reduce EndPoint & init it
write8(padapter, 0x102500ab, read8(padapter, 0x102500ab)|BIT(6)|BIT(7));
#endif
//consideration of power consumption - init
write8(padapter, 0x10250008, read8(padapter, 0x10250008)&0xfffffffb);
}
else if(pregistrypriv->chip_version == RTL8712_1stCUT)
{
//Initialization for power on sequence, Revised by Roger. 2008.09.03.
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, SPS0_CTRL+1, 0x53);
write8(padapter, SPS0_CTRL, 0x57);
//Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
val8 = read8(padapter, AFE_MISC);
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN));
//Enable LDOA15 block
val8 = read8(padapter, LDOA15_CTRL);
write8(padapter, LDOA15_CTRL, (val8|LDA15_EN));
val8 = read8(padapter, SPS1_CTRL);
write8(padapter, SPS1_CTRL, (val8|SPS1_LDEN));
msleep_os(2);
//Enable Switch Regulator Block
val8 = read8(padapter, SPS1_CTRL);
write8(padapter, SPS1_CTRL, (val8|SPS1_SWEN));
write32(padapter, SPS1_CTRL, 0x00a7b267);//?
val8 = read8(padapter, SYS_ISO_CTRL+1);
write8(padapter, SYS_ISO_CTRL+1, (val8|0x08));
//Engineer Packet CP test Enable
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x20));
val8 = read8(padapter, SYS_ISO_CTRL+1);
write8(padapter, SYS_ISO_CTRL+1, (val8& 0x6F));
//Enable AFE clock
val8 = read8(padapter, AFE_XTAL_CTRL+1);
write8(padapter, AFE_XTAL_CTRL+1, (val8& 0xfb));
//Enable AFE PLL Macro Block
val8 = read8(padapter, AFE_PLL_CTRL);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
//Attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, SYS_ISO_CTRL);
write8(padapter, SYS_ISO_CTRL, (val8&0xEE));
// Switch to 40M clock
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8 & (~ SYS_CLKSEL));
//SSC Disable
val8 = read8(padapter, SYS_CLKR);
//write8(padapter, SYS_CLKR, (val8&0x5f));
//Enable MAC clock
val8 = read8(padapter, SYS_CLKR+1);
write8(padapter, SYS_CLKR+1, (val8|0x18));
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, PMC_FSM, 0x02);
//Enable Core digital and enable IOREG R/W
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x08));
//Enable REG_EN
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x80));
//Switch the control path to FW
val8 = read8(padapter, SYS_CLKR+1);
write8(padapter, SYS_CLKR+1, (val8|0x80)& 0xBF);
write8(padapter, CR, 0xFC);
write8(padapter, CR+1, 0x37);
//Fix the RX FIFO issue(usb error), 970410
val8 = read8(padapter, 0x1025FE5c);
write8(padapter, 0x1025FE5c, (val8|BIT(7)));
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
val8 = read8(padapter, 0x102500ab);
write8(padapter, 0x102500ab, (val8|BIT(6)|BIT(7)));
#endif
//For power save, used this in the bit file after 970621
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8&(~CPU_CLKSEL));
}
else if(pregistrypriv->chip_version == RTL8712_2ndCUT || pregistrypriv->chip_version == RTL8712_3rdCUT)
{
//Initialization for power on sequence, Revised by Roger. 2008.09.03.
//E-Fuse leakage prevention sequence
write8(padapter, 0x37, 0xb0);
msleep_os(10);
write8(padapter, 0x37, 0x30);
//
//<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
// MAC I/O to solve FW download fail when system from resume sate.
// 2008.11.04.
//
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
if(val8 & 0x80)
{
val8 &= 0x3f;
write8(padapter, SYS_CLKR+1, val8);
}
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
val8 &= 0x73;
write8(padapter, SYS_FUNC_EN+1, val8);
udelay_os(1000);
//msleep_os(100);//PlatformStallExecution(1000);
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, SPS0_CTRL+1, 0x53);
write8(padapter, SPS0_CTRL, 0x57);// Switching 18V to PWM.
//DbgPrint("SPS0_CTRL+1=0x%x\n", read8(padapter, SPS0_CTRL+1));
//DbgPrint("SPS0_CTRL=0x%x\n", read8(padapter, SPS0_CTRL));
//Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
val8 = read8(padapter, AFE_MISC);
//DbgPrint("AFE_MISC=0x%x\n", val8);
//write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN));
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN)); //Bandgap
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN | AFE_MISC_I32_EN)); //Mbios
//Enable LDOA15 block -> //Enable PLL Power (LDOA15V)
val8 = read8(padapter, LDOA15_CTRL);
//DbgPrint("LDOA15_CTRL=0x%x\n", val8);
write8(padapter, LDOA15_CTRL, (val8|LDA15_EN));
//val8 = read8(padapter, SPS1_CTRL);
//write8(padapter, SPS1_CTRL, (val8|SPS1_LDEN));
//msleep_os(2);
//Enable LDOV12D block
val8 = read8(padapter, LDOV12D_CTRL);
//DbgPrint("LDOV12D_CTRL=0x%x\n", val8);
write8(padapter, LDOV12D_CTRL, (val8|LDV12_EN));
//Enable Switch Regulator Block
//val8 = read8(padapter, SPS1_CTRL);
//write8(padapter, SPS1_CTRL, (val8|SPS1_SWEN));
//write32(padapter, SPS1_CTRL, 0x00a7b267);//?
val8 = read8(padapter, SYS_ISO_CTRL+1);
//DbgPrint("SYS_ISO_CTRL+1=0x%x\n", val8);
write8(padapter, SYS_ISO_CTRL+1, (val8|0x08));
//Engineer Packet CP test Enable
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x20));
//Support 64k IMEM, suggested by SD1 Alex.
val8 = read8(padapter, SYS_ISO_CTRL+1);
//DbgPrint("SYS_ISO_CTRL+1=0x%x\n", val8);
//write8(padapter, SYS_ISO_CTRL+1, (val8& 0x6F));
write8(padapter, SYS_ISO_CTRL+1, (val8&0x68));
//Enable AFE clock
val8 = read8(padapter, AFE_XTAL_CTRL+1);
//DbgPrint("AFE_XTAL_CTRL+1=0x%x\n", val8);
write8(padapter, AFE_XTAL_CTRL+1, (val8& 0xfb));
//Enable AFE PLL Macro Block
val8 = read8(padapter, AFE_PLL_CTRL);
//DbgPrint("AFE_PLL_CTRL=0x%x\n", val8);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
//(20090928) for some sample will download fw failure
udelay_os(1000);
write8(padapter, AFE_PLL_CTRL, (val8|0x51));
udelay_os(100);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
udelay_os(100);
//Attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, SYS_ISO_CTRL);
//DbgPrint("SYS_ISO_CTRL=0x%x\n", val8);
write8(padapter, SYS_ISO_CTRL, (val8&0xEE));
// Switch to 40M clock
write8(padapter, SYS_CLKR, 0x00);
//CPU Clock and 80M Clock SSC Disable to overcome FW download fail timing issue.
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, (val8|0xa0));
//Enable MAC clock
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
write8(padapter, SYS_CLKR+1, (val8|0x18));
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, PMC_FSM, 0x02);
//DbgPrint("PMC_FSM=0x%x\n", read8(padapter, PMC_FSM));
//Enable Core digital and enable IOREG R/W
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x08));
//Enable REG_EN
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x80));
//Switch the control path to FW
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
write8(padapter, SYS_CLKR+1, (val8|0x80)& 0xBF);
write8(padapter, CR, 0xFC);
write8(padapter, CR+1, 0x37);
//Fix the RX FIFO issue(usb error), 970410
val8 = read8(padapter, 0x1025FE5c);
//DbgPrint("0x1025FE5c=0x%x\n", val8);
write8(padapter, 0x1025FE5c, (val8|BIT(7)));
#if 0 //fw will help set it depending on the fwpriv.
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
val8 = read8(padapter, 0x102500ab);
write8(padapter, 0x102500ab, (val8|BIT(6)|BIT(7)));
#endif
#endif
//For power save, used this in the bit file after 970621
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8&(~CPU_CLKSEL));
//DbgPrint("SYS_CLKR=0x%x\n", read8(padapter, SYS_CLKR));
// Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
write8(padapter, 0x1025fe1c, 0x80);
//
// <Roger_EXP> To make sure that TxDMA can ready to download FW.
// We should reset TxDMA if IMEM RPT was not ready.
// Suggested by SD1 Alex. 2008.10.23.
//
do
{
val8 = read8(padapter, TCR);
if((val8 & _TXDMA_INIT_VALUE) == _TXDMA_INIT_VALUE)
break;
udelay_os(5);//PlatformStallExecution(5);
}while(PollingCnt--); // Delay 1ms
if(PollingCnt <= 0 )
{
//ERR_8712("MacConfigBeforeFwDownloadASIC(): Polling _TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", val8);
val8 = read8(padapter, CR);
write8(padapter, CR, val8&(~_TXDMA_EN));
udelay_os(2);//PlatformStallExecution(2);
write8(padapter, CR, val8|_TXDMA_EN);// Reset TxDMA
}
}
else
{
ret = _FAIL;
}
return ret;
}
u8 usb_hal_bus_init(_adapter * padapter){
u32 val32;
u8 tmp8,val8=_SUCCESS;
// u16 i = 0;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
// NDIS_STATUS ndisstatus=NDIS_STATUS_SUCCESS;
_func_enter_;
//************************************************************************************************************
// Initialization for USB
//************************************************************************************************************
//SET_SYSCLK to 40M
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_SYSCLK, 0, 0, &tmp8, 1, _TRUE);
DEBUG_ERR(("usb_hal_bus_init() : System Clock = %d\n", tmp8));
if (tmp8 > 0){
DEBUG_ERR(("usb_hal_bus_init() : System Clock = is High Speed, no necessary to set again.tmp8=0x%x\n", tmp8));
} else {
DEBUG_ERR(("usb_hal_bus_init() : Set System Clock to 40MHz.\n"));
usbvendorrequest(&padapter->dvobjpriv, RT_USB_SET_SYSCLK, RT_USB_SYSCLK_40MHZ, 0, NULL, 0, _FALSE);
// check the value
msleep_os(100);
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_SYSCLK, 0, 0, &tmp8, 1, _TRUE);
DEBUG_ERR(("usb_hal_bus_init() : System Clock = %d\n", tmp8));
if ( tmp8 != RT_USB_SYSCLK_40MHZ) {
DEBUG_ERR(("usb_hal_bus_init(): System Clock is not matched, GET_SYSCLK = %d",tmp8));
val8 = _FAIL;
goto exit;
}
}
//4 Turn on LDO
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_REGISTER, RT_USB_LDO, 0, &tmp8, 1, _TRUE);
DEBUG_ERR(("usb_hal_bus_init() : LDO = %d\n", tmp8));
if (tmp8 == 0x01){
DEBUG_ERR(("usb_hal_bus_init() : LDO is turned on. No necessary to Turn it on.\n"));
} else {
DEBUG_ERR(("usb_hal_bus_init() : Turn On LDO\n"));
usbvendorrequest(&padapter->dvobjpriv, RT_USB_SET_REGISTER, RT_USB_LDO, RT_USB_LDO_ON, NULL, 0, _FALSE);
msleep_os(100);
usbvendorrequest(&padapter->dvobjpriv, RT_USB_GET_REGISTER, RT_USB_LDO, 0, &tmp8, 1, _TRUE);
if(tmp8 != 0x01){
DEBUG_ERR(("usb_hal_bus_init() : LDO can't turn on.\n"));
DEBUG_ERR(("usb_hal_bus_init() : LDO = %d\n", tmp8));
val8 = _FAIL;
goto exit;
}
DEBUG_ERR(("usb_hal_bus_init() : LDO = %d\n", tmp8));
}
DEBUG_ERR(("before read SYSCLKR!\n"));
DEBUG_ERR(("bSupriseRemoved=%x! bDriverstopped=%x!\n",padapter->bSurpriseRemoved,padapter->bDriverStopped));
val32 = read32(padapter, SYSCLKR);
DEBUG_ERR(("^^^^^^^^^SYSCLKR : %.8x !\n", val32));
if(padapter->bDriverStopped){
DEBUG_ERR(("padapter->bDriverStopped=%d !\n", padapter->bDriverStopped));
val8=_FAIL;
}
if (pregistrypriv->chip_version == RTL8711_FPGA)
write32(padapter, SYSCLKR, (val32 | _LXBUS0S | _HWMASK | _HSSEL));
else
write32(padapter, SYSCLKR, (val32 | _HWMASK | _HSSEL));
if (pregistrypriv->chip_version == RTL8711_FPGA)
{
pregistrypriv->chip_version = RTL8711_FPGA;
}
else
{
//determine the chip version
if(val32&BIT(31))
{
pregistrypriv->chip_version = RTL8711_3rdCUT;
DEBUG_ERR(("usb_hal_bus_init:RTL8711_3rdCUT\n"));
}
else
{
//try again
val32 = read32(padapter, SYSCLKR);
if(val32&BIT(31))
{
pregistrypriv->chip_version = RTL8711_3rdCUT;
DEBUG_ERR(("usb_hal_bus_init(2nd time):RTL8711_3rdCUT\n"));
}
else{
val32 = read32(padapter, AFEBYPS_CFG);
if(val32&BIT(0))
{
pregistrypriv->chip_version = RTL8711_2ndCUT;
DEBUG_ERR(("usb_hal_bus_init:RTL8711_2ndCUT\n"));
}
else
{
pregistrypriv->chip_version = RTL8711_1stCUT;
DEBUG_ERR(("usb_hal_bus_init:RTL8711_1stCUT\n"));
}
}
}
}
val32 = read32(padapter, SYSCLKR);
DEBUG_ERR(("^^^^^^^^^SYSCLKR : %.8x !\n", val32));
DEBUG_ERR(("Turn _SCRST | _UARTRST | BIT(3) !"));
val32 = read32(padapter, SYSCTRL);
write32(padapter, SYSCTRL, (val32 |_SCRST | _UARTRST | BIT(3)));
msleep_os(200); //delay
val32= read32(padapter, SYSCTRL);
DEBUG_INFO(("^^^^^^^^^SYSCTRL : %x !\n", val32));
exit:
_func_exit_;
return val8;
}
