void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
int i, cpu, value;
void __iomem *cpu_ptr;
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
scu_enable(scu_base_addr());
cpu_ptr = ioremap_nocache(MSM8625_CPU_PHYS, SZ_8);
if (!cpu_ptr) {
pr_err("failed to ioremap for secondary cores\n");
return;
}
msm8625_boot_vector_init(cpu_ptr,
virt_to_phys(msm_secondary_startup));
iounmap(cpu_ptr);
for_each_possible_cpu(cpu) {
switch (cpu) {
case 0:
break;
case 1:
remapper_address(MSM8625_CPU_PHYS, 0x34);
per_cpu_data(cpu, 0x0, 0x3c,
MSM8625_INT_ACSR_MP_CORE_IPC1);
enable_boot_remapper(BIT(26), 0x30);
break;
case 2:
remapper_address((MSM8625_CPU_PHYS >> 16), 0x4C);
per_cpu_data(cpu, 0x8, 0x50,
MSM8625_INT_ACSR_MP_CORE_IPC2);
enable_boot_remapper(BIT(25), 0x48);
break;
case 3:
value = __raw_readl(MSM_CFG_CTL_BASE + 0x4C);
remapper_address(value | MSM8625_CPU_PHYS, 0x4C);
per_cpu_data(cpu, 0xC, 0x50,
MSM8625_INT_ACSR_MP_CORE_IPC3);
enable_boot_remapper(BIT(26), 0x48);
break;
}
}
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
int i, value;
void __iomem *second_ptr;
/*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time.
*/
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
scu_enable(scu_base_addr());
/*
* Write the address of secondary startup into the
* boot remapper register. The secondary CPU branches to this address.
*/
__raw_writel(MSM8625_SECONDARY_PHYS, (MSM_CFG_CTL_BASE + 0x34));
mb();
second_ptr = ioremap_nocache(MSM8625_SECONDARY_PHYS, SZ_8);
if (!second_ptr) {
pr_err("failed to ioremap for secondary core\n");
return;
}
msm8625_boot_vector_init(second_ptr,
virt_to_phys(msm_secondary_startup));
iounmap(second_ptr);
/* Enable boot remapper address: bit 26 for core1 */
value = __raw_readl(MSM_CFG_CTL_BASE + 0x30);
__raw_writel(value | (0x4 << 24), MSM_CFG_CTL_BASE + 0x30) ;
mb();
}
