static int __init msm_setup_fiq_handler(void)
{
int i, ret = 0;
spin_lock_init(&msm_fiq_lock);
claim_fiq(&msm7k_fh);
set_fiq_handler(&msm7k_fiq_start, msm7k_fiq_length);
for_each_possible_cpu(i) {
msm7k_fiq_stack[i] = (void *)__get_free_pages(GFP_KERNEL,
THREAD_SIZE_ORDER);
if (msm7k_fiq_stack[i] == NULL)
break;
}
if (i != nr_cpumask_bits) {
pr_err("FIQ STACK SETUP IS NOT SUCCESSFUL\n");
for (i = 0; i < nr_cpumask_bits && msm7k_fiq_stack[i] != NULL;
i++)
free_pages((unsigned long)msm7k_fiq_stack[i],
THREAD_SIZE_ORDER);
return -ENOMEM;
}
fiq_set_type(msm_fiq_no, IRQF_TRIGGER_RISING);
if (cpu_is_msm8625() || cpu_is_msm8625q())
gic_set_irq_secure(msm_fiq_no);
else
msm_fiq_select(msm_fiq_no);
enable_irq(msm_fiq_no);
pr_info("%s : MSM FIQ handler setup--done\n", __func__);
return ret;
}
void msm_serial_debug_init(unsigned int base, int irq,
struct device *clk_device, int signal_irq)
{
int ret;
void *port;
debug_clk = clk_get(clk_device, "uart_clk");
if (debug_clk)
clk_enable(debug_clk);
port = ioremap(base, 4096);
if (!port)
return;
init_data.base = base;
init_data.irq = irq;
init_data.clk_device = clk_device;
init_data.signal_irq = signal_irq;
debug_port_base = (unsigned int) port;
debug_signal_irq = signal_irq;
debug_port_init();
debug_prompt();
msm_fiq_select(irq);
msm_fiq_set_handler(debug_fiq, 0);
msm_fiq_enable(irq);
ret = request_irq(signal_irq, debug_irq,
IRQF_TRIGGER_RISING, "debug", 0);
if (ret)
printk(KERN_ERR
"serial_debugger: could not install signal_irq");
#if defined(CONFIG_MSM_SERIAL_DEBUGGER_CONSOLE)
register_console(&msm_serial_debug_console);
#endif
debugger_enable = 1;
}
void __init msm_init_sirc(void)
{
int i;
int_enable = 0;
wake_enable = 0;
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
sirc_irq_handler);
irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
#if defined(CONFIG_MSM_FIQ_SUPPORT)
msm_fiq_select(sirc_reg_table[i].cascade_fiq);
msm_fiq_enable(sirc_reg_table[i].cascade_fiq);
#endif
}
return;
}
