void msm_irq_exit_sleep1(void)
{
int i;
msm_irq_ack(INT_A9_M2A_6);
msm_irq_ack(INT_PWB_I2C);
for (i = 0; i < VIC_NUM_BANKS; i++) {
writel(msm_irq_shadow_reg[i].int_type, VIC_INT_TYPE(i));
writel(msm_irq_shadow_reg[i].int_polarity, VIC_INT_POLARITY(i));
writel(msm_irq_shadow_reg[i].int_en[0], VIC_INT_EN(i));
writel(msm_irq_shadow_reg[i].int_select, VIC_INT_SELECT(i));
}
writel(3, VIC_INT_MASTEREN);
if (!smsm_int_info) {
printk(KERN_ERR "msm_irq_exit_sleep <SM NO INT_INFO>\n");
return;
}
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP) {
printk(KERN_INFO "%s %x %x %x now", __func__,
smsm_int_info->interrupt_mask,
smsm_int_info->pending_interrupts,
smsm_int_info->wakeup_reason);
print_vic_irq_stat();
}
}
/*
* Restore interrupt subsystem from sleep -- phase 1.
* Configure interrupt hardware.
*/
void msm_irq_exit_sleep1(uint32_t irq_mask, uint32_t wakeup_reason,
uint32_t pending_irqs)
{
int i;
msm_irq_ack(INT_A9_M2A_6);
for (i = 0; i < VIC_NUM_REGS; i++) {
writel(msm_irq_shadow_reg[i].int_type,
VIC_INT_TYPE0 + i * 4);
writel(msm_irq_shadow_reg[i].int_polarity,
VIC_INT_POLARITY0 + i * 4);
writel(msm_irq_shadow_reg[i].int_en[0],
VIC_INT_EN0 + i * 4);
writel(msm_irq_shadow_reg[i].int_select,
VIC_INT_SELECT0 + i * 4);
}
writel(3, VIC_INT_MASTEREN);
dsb();
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
DPRINT_REGS(VIC_IRQ_STATUS, "%s %x %x %x now",
__func__, irq_mask, pending_irqs, wakeup_reason);
}
/*
* Restore interrupt subsystem from sleep -- phase 1.
* Configure interrupt hardware.
*/
void msm_irq_exit_sleep1(uint32_t irq_mask, uint32_t wakeup_reason,
uint32_t pending_irqs)
{
int i;
msm_irq_ack(INT_A9_M2A_6);
for (i = 0; i < 2; i++) {
writel(msm_irq_shadow_reg[i].int_type,
VIC_INT_TYPE0 + i * 4);
writel(msm_irq_shadow_reg[i].int_polarity,
VIC_INT_POLARITY0 + i * 4);
writel(msm_irq_shadow_reg[i].int_en[0],
VIC_INT_EN0 + i * 4);
writel(msm_irq_shadow_reg[i].int_select,
VIC_INT_SELECT0 + i * 4);
}
writel(3, VIC_INT_MASTEREN);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
printk(KERN_INFO "%s %x %x %x now %x %x\n",
__func__, irq_mask, pending_irqs, wakeup_reason,
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
}
int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
{
int limit = 10;
uint32_t pending0, pending1;
if (from_idle && !arm9_wake)
return 0;
/* edge triggered interrupt may get lost if this mode is used */
WARN_ON_ONCE(!arm9_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
printk(KERN_INFO "msm_irq_enter_sleep change irq, pend %x %x\n",
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
pending0 = readl(VIC_IRQ_STATUS0);
pending1 = readl(VIC_IRQ_STATUS1);
pending0 &= msm_irq_shadow_reg[0].int_en[!from_idle];
/* Clear INT_A9_M2A_5 since requesting sleep triggers it */
pending0 &= ~(1U << INT_A9_M2A_5);
pending1 &= msm_irq_shadow_reg[1].int_en[!from_idle];
if (pending0 || pending1) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT)
printk(KERN_INFO "msm_irq_enter_sleep2 abort %x %x\n",
pending0, pending1);
return -EAGAIN;
}
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "msm_irq_enter_sleep cleared "
"int %d (%d)\n", irq, pend_irq);
}
if (arm9_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
msm_irq_ack(INT_A9_M2A_6);
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET0);
} else {
writel(msm_irq_shadow_reg[0].int_en[1], VIC_INT_ENSET0);
writel(msm_irq_shadow_reg[1].int_en[1], VIC_INT_ENSET1);
}
return 0;
}
void msm_irq_exit_sleep1(void)
{
int i;
msm_irq_ack(INT_A9_M2A_6);
msm_irq_ack(INT_PWB_I2C);
for (i = 0; i < 2; i++) {
writel(msm_irq_shadow_reg[i].int_type, VIC_INT_TYPE0 + i * 4);
writel(msm_irq_shadow_reg[i].int_polarity, VIC_INT_POLARITY0 + i * 4);
writel(msm_irq_shadow_reg[i].int_en[0], VIC_INT_EN0 + i * 4);
writel(msm_irq_shadow_reg[i].int_select, VIC_INT_SELECT0 + i * 4);
}
writel(3, VIC_INT_MASTEREN);
if (!smsm_int_info) {
printk(KERN_ERR "msm_irq_exit_sleep <SM NO INT_INFO>\n");
return;
}
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP)
printk(KERN_INFO "msm_irq_exit_sleep1 %x %x %x now %x %x\n",
smsm_int_info->interrupt_mask,
smsm_int_info->pending_interrupts,
smsm_int_info->wakeup_reason,
readl(VIC_IRQ_STATUS0), readl(VIC_IRQ_STATUS1));
}
int msm_irq_enter_sleep2(bool arm9_wake, int from_idle)
{
int limit = 10;
uint32_t pending[VIC_NUM_BANKS];
int i;
uint32_t any = 0;
if (from_idle && !arm9_wake)
return 0;
/* edge triggered interrupt may get lost if this mode is used */
WARN_ON_ONCE(!arm9_wake && !from_idle);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP) {
printk(KERN_INFO "%s: change irq, pend", __func__);
print_vic_irq_stat();
}
for (i = 0; i < VIC_NUM_BANKS; ++i) {
pending[i] = readl(VIC_IRQ_STATUS(i));
pending[i] &= msm_irq_shadow_reg[i].int_en[!from_idle];
/* Clear INT_A9_M2A_5 since requesting sleep triggers it */
if (i == (INT_A9_M2A_5 / 32))
pending[i] &= ~(1U << (INT_A9_M2A_5 % 32));
any |= pending[i];
}
if (any) {
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_ABORT) {
printk(KERN_INFO "%s abort", __func__);
print_irq_array(pending, VIC_NUM_BANKS);
}
return -EAGAIN;
}
for (i = 0; i < VIC_NUM_BANKS; ++i)
writel(0, VIC_INT_EN(i));
while (limit-- > 0) {
int pend_irq;
int irq = readl(VIC_IRQ_VEC_RD);
if (irq == -1)
break;
pend_irq = readl(VIC_IRQ_VEC_PEND_RD);
if (msm_irq_debug_mask & IRQ_DEBUG_SLEEP_INT)
printk(KERN_INFO "msm_irq_enter_sleep cleared "
"int %d (%d)\n", irq, pend_irq);
}
if (arm9_wake) {
msm_irq_set_type(INT_A9_M2A_6, IRQF_TRIGGER_RISING);
msm_irq_ack(INT_A9_M2A_6);
writel(1U << INT_A9_M2A_6, VIC_INT_ENSET(0));
} else {
for (i = 0; i < VIC_NUM_BANKS; ++i)
writel(msm_irq_shadow_reg[i].int_en[1],
VIC_INT_ENSET(i));
}
return 0;
}
void dpram_irq_clear(void)
{
msm_irq_ack(INT_A9_M2A_4);
}
