static void msm_snddev_dmic_power(int en) { pr_aud_err("%s", __func__); if (en) msm_snddev_enable_dmic_power(); else msm_snddev_disable_dmic_power(); }
static void msm_snddev_enable_dmic_sec_power(void) { pr_aud_err("%s", __func__); msm_snddev_enable_dmic_power(); #ifdef CONFIG_PMIC8058_OTHC pm8058_micbias_enable(OTHC_MICBIAS_2, OTHC_SIGNAL_ALWAYS_ON); #endif }
static int msm_snddev_enable_dmic_sec_power(void) { int ret; pr_aud_err("%s", __func__); ret = msm_snddev_enable_dmic_power(); if (ret) { pr_err("%s: Error: Enabling dmic power failed\n", __func__); return ret; } #ifdef CONFIG_PMIC8058_OTHC ret = pm8058_micbias_enable(OTHC_MICBIAS_2, OTHC_SIGNAL_ALWAYS_ON); if (ret) { pr_err("%s: Error: Enabling micbias failed\n", __func__); msm_snddev_disable_dmic_power(); return ret; } #endif return 0; }
static int msm8660_startup(struct snd_pcm_substream *substream) { int ret = 0; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { rx_osr_clk = clk_get(NULL, "i2s_spkr_osr_clk"); if (IS_ERR(rx_osr_clk)) { pr_debug("Failed to get i2s_spkr_osr_clk\n"); return PTR_ERR(rx_osr_clk); } /* Master clock OSR 256 */ /* Initially set to Lowest sample rate Needed */ clk_set_rate(rx_osr_clk, 8000 * 256); ret = clk_prepare_enable(rx_osr_clk); if (ret != 0) { pr_debug("Unable to enable i2s_spkr_osr_clk\n"); clk_put(rx_osr_clk); return ret; } rx_bit_clk = clk_get(NULL, "i2s_spkr_bit_clk"); if (IS_ERR(rx_bit_clk)) { pr_debug("Failed to get i2s_spkr_bit_clk\n"); clk_disable_unprepare(rx_osr_clk); clk_put(rx_osr_clk); return PTR_ERR(rx_bit_clk); } clk_set_rate(rx_bit_clk, 8); ret = clk_prepare_enable(rx_bit_clk); if (ret != 0) { pr_debug("Unable to enable i2s_spkr_bit_clk\n"); clk_put(rx_bit_clk); clk_disable_unprepare(rx_osr_clk); clk_put(rx_osr_clk); return ret; } timpani_poweramp_on(); msleep(30); /* End of platform specific logic */ } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { tx_osr_clk = clk_get(NULL, "i2s_mic_osr_clk"); if (IS_ERR(tx_osr_clk)) { pr_debug("Failed to get i2s_mic_osr_clk\n"); return PTR_ERR(tx_osr_clk); } /* Master clock OSR 256 */ clk_set_rate(tx_osr_clk, 8000 * 256); ret = clk_prepare_enable(tx_osr_clk); if (ret != 0) { pr_debug("Unable to enable i2s_mic_osr_clk\n"); clk_put(tx_osr_clk); return ret; } tx_bit_clk = clk_get(NULL, "i2s_mic_bit_clk"); if (IS_ERR(tx_bit_clk)) { pr_debug("Failed to get i2s_mic_bit_clk\n"); clk_disable_unprepare(tx_osr_clk); clk_put(tx_osr_clk); return PTR_ERR(tx_bit_clk); } clk_set_rate(tx_bit_clk, 8); ret = clk_prepare_enable(tx_bit_clk); if (ret != 0) { pr_debug("Unable to enable i2s_mic_bit_clk\n"); clk_put(tx_bit_clk); clk_disable_unprepare(tx_osr_clk); clk_put(tx_osr_clk); return ret; } msm_snddev_enable_dmic_power(); msleep(30); } return ret; }