int mt76_mcu_load_cr(struct mt76_dev *dev, u8 type, u8 temp_level, u8 channel)
{
struct sk_buff *skb;
struct {
u8 cr_mode;
u8 temp;
u8 ch;
u8 _pad0;
__le32 cfg;
} __packed __aligned(4) msg = {
.cr_mode = type,
.temp = temp_level,
.ch = channel,
};
u32 val;
val = BIT(31);
val |= (mt76_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff;
val |= (mt76_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00;
msg.cfg = cpu_to_le32(val);
/* first set the channel without the extension channel info */
skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
return mt76_mcu_msg_send(dev, skb, CMD_LOAD_CR);
}
static u8
mt76_get_5g_rx_gain(struct mt76_dev *dev, u8 channel)
{
enum mt76_cal_channel_group group = mt76_get_cal_channel_group(channel);
switch (group) {
case MT_CH_5G_JAPAN:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
case MT_CH_5G_UNII_1:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
case MT_CH_5G_UNII_2:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
case MT_CH_5G_UNII_2E_1:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
case MT_CH_5G_UNII_2E_2:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
default:
return mt76_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
}
}
static void
mt76_fixup_xtal(struct mt76_dev *dev)
{
u16 eep_val;
s8 offset = 0;
eep_val = mt76_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
offset = eep_val & 0x7f;
if ((eep_val & 0xff) == 0xff)
offset = 0;
else if (eep_val & 0x80)
offset = 0 - offset;
eep_val >>= 8;
if (eep_val == 0x00 || eep_val == 0xff) {
eep_val = mt76_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
eep_val &= 0xff;
if (eep_val == 0x00 || eep_val == 0xff)
eep_val = 0x14;
}
eep_val &= 0x7f;
mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
eep_val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_2);
switch (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
case 0:
mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
break;
case 1:
mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
break;
default:
break;
}
}
int mt76_phy_set_channel(struct mt76_dev *dev,
struct cfg80211_chan_def *chandef)
{
struct ieee80211_channel *chan = chandef->chan;
bool scan = test_bit(MT76_SCANNING, &dev->state);
enum ieee80211_band band = chan->band;
u8 channel;
u32 ext_cca_chan[4] = {
[0] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 0) |
MT76_SET(MT_EXT_CCA_CFG_CCA1, 1) |
MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) |
MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) |
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
[1] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 1) |
MT76_SET(MT_EXT_CCA_CFG_CCA1, 0) |
MT76_SET(MT_EXT_CCA_CFG_CCA2, 2) |
MT76_SET(MT_EXT_CCA_CFG_CCA3, 3) |
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
[2] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 2) |
MT76_SET(MT_EXT_CCA_CFG_CCA1, 3) |
MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) |
MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) |
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
[3] = MT76_SET(MT_EXT_CCA_CFG_CCA0, 3) |
MT76_SET(MT_EXT_CCA_CFG_CCA1, 2) |
MT76_SET(MT_EXT_CCA_CFG_CCA2, 1) |
MT76_SET(MT_EXT_CCA_CFG_CCA3, 0) |
MT76_SET(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
};
int ch_group_index;
u8 bw, bw_index;
int freq, freq1;
int ret;
u8 sifs = 13;
dev->chandef = *chandef;
dev->cal.channel_cal_done = false;
freq = chandef->chan->center_freq;
freq1 = chandef->center_freq1;
channel = chan->hw_value;
switch (chandef->width) {
case NL80211_CHAN_WIDTH_40:
bw = 1;
if (freq1 > freq) {
bw_index = 1;
ch_group_index = 0;
} else {
bw_index = 3;
ch_group_index = 1;
}
channel += 2 - ch_group_index * 4;
break;
case NL80211_CHAN_WIDTH_80:
ch_group_index = (freq - freq1 + 30) / 20;
if (WARN_ON(ch_group_index < 0 || ch_group_index > 3))
ch_group_index = 0;
bw = 2;
bw_index = ch_group_index;
channel += 6 - ch_group_index * 4;
break;
default:
bw = 0;
bw_index = 0;
ch_group_index = 0;
break;
}
mt76_read_rx_gain(dev);
mt76_phy_set_txpower_regs(dev, band);
mt76_configure_tx_delay(dev, band, bw);
mt76_phy_set_txpower(dev);
mt76_apply_rate_power_table(dev);
mt76_set_rx_chains(dev);
mt76_phy_set_band(dev, chan->band, ch_group_index & 1);
mt76_phy_set_bw(dev, chandef->width, ch_group_index);
mt76_set_tx_dac(dev);
mt76_rmw(dev, MT_EXT_CCA_CFG,
(MT_EXT_CCA_CFG_CCA0 |
MT_EXT_CCA_CFG_CCA1 |
MT_EXT_CCA_CFG_CCA2 |
MT_EXT_CCA_CFG_CCA3 |
MT_EXT_CCA_CFG_CCA_MASK),
ext_cca_chan[ch_group_index]);
if (chandef->width >= NL80211_CHAN_WIDTH_40)
sifs++;
mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, sifs);
ret = mt76_mcu_set_channel(dev, channel, bw, bw_index, scan);
if (ret)
return ret;
mt76_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
/* Enable LDPC Rx */
if (mt76xx_rev(dev) >= MT76XX_REV_E3)
mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
if (!dev->cal.init_cal_done) {
u8 val = mt76_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
if (val != 0xff)
mt76_mcu_calibrate(dev, MCU_CAL_R, 0);
}
mt76_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
/* Rx LPF calibration */
if (!dev->cal.init_cal_done)
mt76_mcu_calibrate(dev, MCU_CAL_RC, 0);
dev->cal.init_cal_done = true;
mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
if (scan)
return 0;
dev->cal.low_gain = -1;
mt76_phy_channel_calibrate(dev, true);
mt76_get_agc_gain(dev, dev->cal.agc_gain_init);
ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
MT_CALIBRATE_INTERVAL);
return 0;
}
static void
mt76_phy_tssi_compensate(struct mt76_dev *dev)
{
struct ieee80211_channel *chan = dev->chandef.chan;
struct mt76_tx_power_info txp;
struct mt76_tssi_comp t = {};
if (!dev->cal.tssi_cal_done)
return;
if (dev->cal.tssi_comp_done) {
/* TSSI trigger */
t.cal_mode = BIT(0);
mt76_mcu_tssi_comp(dev, &t);
} else {
if (!(mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)))
return;
mt76_get_power_info(dev, &txp);
if (mt76_ext_pa_enabled(dev, chan->band))
t.pa_mode = 1;
t.cal_mode = BIT(1);
t.slope0 = txp.chain[0].tssi_slope;
t.offset0 = txp.chain[0].tssi_offset;
t.slope1 = txp.chain[1].tssi_slope;
t.offset1 = txp.chain[1].tssi_offset;
dev->cal.tssi_comp_done = true;
mt76_mcu_tssi_comp(dev, &t);
if (t.pa_mode || dev->cal.dpd_cal_done)
return;
msleep(10);
mt76_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
dev->cal.dpd_cal_done = true;
}
}
static void
mt76_phy_temp_compensate(struct mt76_dev *dev)
{
struct mt76_temp_comp t;
int temp, db_diff;
if (mt76_get_temp_comp(dev, &t))
return;
temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
temp -= t.temp_25_ref;
temp = (temp * 1789) / 1000 + 25;
dev->cal.temp = temp;
if (temp > 25)
db_diff = (temp - 25) / t.high_slope;
else
db_diff = (25 - temp) / t.low_slope;
db_diff = min(db_diff, t.upper_bound);
db_diff = max(db_diff, t.lower_bound);
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
db_diff * 2);
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
db_diff * 2);
}
void mt76_phy_calibrate(struct work_struct *work)
{
struct mt76_dev *dev;
dev = container_of(work, struct mt76_dev, cal_work.work);
mt76_phy_channel_calibrate(dev, false);
mt76_phy_tssi_compensate(dev);
mt76_phy_temp_compensate(dev);
mt76_phy_update_channel_gain(dev);
ieee80211_queue_delayed_work(dev->hw, &dev->cal_work,
MT_CALIBRATE_INTERVAL);
}
int mt76_phy_start(struct mt76_dev *dev)
{
int ret;
ret = mt76_mcu_set_radio_state(dev, true);
if (ret)
return ret;
mt76_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
return ret;
}
static int
mt76pci_load_firmware(struct mt76_dev *dev)
{
const struct firmware *fw;
const struct mt76_fw_header *hdr;
int i, len, ret;
__le32 *cur;
u32 offset, val;
ret = request_firmware(&fw, MT7662_FIRMWARE, dev->dev);
if (ret)
return ret;
if (!fw || !fw->data || fw->size < sizeof(*hdr))
goto error;
hdr = (const struct mt76_fw_header *) fw->data;
len = sizeof(*hdr);
len += le32_to_cpu(hdr->ilm_len);
len += le32_to_cpu(hdr->dlm_len);
if (fw->size != len)
goto error;
val = le16_to_cpu(hdr->fw_ver);
printk("Firmware Version: %d.%d.%02d\n",
(val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf);
val = le16_to_cpu(hdr->build_ver);
printk("Build: %x\n", val);
printk("Build Time: %.16s\n", hdr->build_time);
cur = (__le32 *) (fw->data + sizeof(*hdr));
len = le32_to_cpu(hdr->ilm_len);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_ILM_OFFSET);
write_data(dev, MT_MCU_ILM_ADDR, cur, len);
cur += len / sizeof(*cur);
len = le32_to_cpu(hdr->dlm_len);
if (mt76xx_rev(dev) >= MT76XX_REV_E3)
offset = MT_MCU_DLM_ADDR_E3;
else
offset = MT_MCU_DLM_ADDR;
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, MT_MCU_DLM_OFFSET);
write_data(dev, offset, cur, len);
mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
val = mt76_eeprom_get(dev, MT_EE_NIC_CONF_2);
if (MT76_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
mt76_set(dev, MT_MCU_COM_REG0, BIT(30));
/* trigger firmware */
mt76_wr(dev, MT_MCU_INT_LEVEL, 2);
for (i = 200; i > 0; i--) {
val = mt76_rr(dev, MT_MCU_COM_REG0);
if (val & 1)
break;
msleep(10);
}
if (!i) {
printk("Firmware failed to start\n");
release_firmware(fw);
return -ETIMEDOUT;
}
printk("Firmware running!\n");
release_firmware(fw);
return ret;
error:
printk("Invalid firmware\n");
release_firmware(fw);
return -ENOENT;
}
