static int __init mt_power_management_init(void) { struct proc_dir_entry *entry = NULL; struct proc_dir_entry *pm_init_dir = NULL; pm_power_off = mt_power_off; #if !defined (CONFIG_MTK_FPGA) //FIXME: for FPGA early porting #if 0 xlog_printk(ANDROID_LOG_INFO, "Power/PM_INIT", "Bus Frequency = %d KHz\n", mt_get_bus_freq()); #endif //cpu dormant driver init // mt_cpu_dormant_init(); // SPM driver init spm_module_init(); // Sleep driver init (for suspend) // slp_module_init(); mt_clkmgr_init(); //mt_pm_log_init(); // power management log init //FIXME: for FPGA early porting // mt_dcm_init(); // dynamic clock management init pm_init_dir = proc_mkdir("pm_init", NULL); pm_init_dir = proc_mkdir("pm_init", NULL); if (!pm_init_dir) { pr_err("[%s]: mkdir /proc/pm_init failed\n", __FUNCTION__); } else { entry = proc_create("cpu_speed_dump", S_IRUGO, pm_init_dir, &cpu_fops); //entry = proc_create("bigcpu_speed_dump", S_IRUGO, pm_init_dir, &bigcpu_fops); entry = proc_create("emi_speed_dump", S_IRUGO, pm_init_dir, &emi_fops); entry = proc_create("bus_speed_dump", S_IRUGO, pm_init_dir, &bus_fops); //entry = proc_create("mmclk_speed_dump", S_IRUGO, pm_init_dir, &mmclk_fops); //entry = proc_create("mfgclk_speed_dump", S_IRUGO, pm_init_dir, &mfgclk_fops); #ifdef TOPCK_LDVT entry = proc_create("abist_meter_test", S_IRUGO|S_IWUSR, pm_init_dir, &abist_meter_fops); entry = proc_create("ckgen_meter_test", S_IRUGO|S_IWUSR, pm_init_dir, &ckgen_meter_fops); #endif } #endif return 0; }
static u32 mt_i2c_get_func_clk(struct mt_i2c_data *i2c) { return (i2c->flags & MT_WRAPPER_BUS) ? (u32)(I2C_CLK_RATE) : (mt_get_bus_freq() / 16); }
static int bus_speed_dump_read(struct seq_file *m, void *v) { seq_printf(m, "%d\n", mt_get_bus_freq()); return 0; }