int config_L2_size(enum options option) { int ret = 0; unsigned long flag; local_irq_save(flag); ret = mt_secure_call(MTK_SIP_KERNEL_L2_SHARING, option, g_l2c_share_info.share_cluster_num, (g_l2c_share_info.cluster_borrow<<16) | (g_l2c_share_info.cluster_return)); local_irq_restore(flag); return ret; }
int __cpuinit mt_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; pr_crit("[AT]Boot slave CPU\n"); atomic_inc(&hotplug_cpu_count); pr_crit("[AT11]Boot slave CPU %d\n",cpu); /* * Set synchronisation state between this boot processor * and the secondary one */ spin_lock(&boot_lock); pr_crit("mt_smp_boot_secondary, cpu: %d\n", cpu); HOTPLUG_INFO("mt_smp_boot_secondary, cpu: %d\n", cpu); /* * The secondary processor is waiting to be released from * the holding pen - release it, then wait for it to flag * that it has been released by resetting pen_release. * * Note that "pen_release" is the hardware CPU ID, whereas * "cpu" is Linux's internal ID. */ /* * This is really belt and braces; we hold unintended secondary * CPUs in the holding pen until we're ready for them. However, * since we haven't sent them a soft interrupt, they shouldn't * be there. */ write_pen_release(cpu); #if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) if(cpu >=1 && cpu <=3) mt_secure_call(MC_FC_SET_RESET_VECTOR, virt_to_phys(mt_secondary_startup), cpu, 0); #else mt_smp_set_boot_addr(virt_to_phys(mt_secondary_startup), cpu); #endif switch(cpu) { case 1: #ifdef CONFIG_MTK_FPGA mt_reg_sync_writel(SLAVE1_MAGIC_NUM, SLAVE1_MAGIC_REG); HOTPLUG_INFO("SLAVE1_MAGIC_NUM:%x\n", SLAVE1_MAGIC_NUM); #endif spm_mtcmos_ctrl_cpu1(STA_POWER_ON, 1); break; case 2: #ifdef CONFIG_MTK_FPGA mt_reg_sync_writel(SLAVE2_MAGIC_NUM, SLAVE2_MAGIC_REG); HOTPLUG_INFO("SLAVE2_MAGIC_NUM:%x\n", SLAVE2_MAGIC_NUM); #endif spm_mtcmos_ctrl_cpu2(STA_POWER_ON, 1); break; case 3: #ifdef CONFIG_MTK_FPGA mt_reg_sync_writel(SLAVE3_MAGIC_NUM, SLAVE3_MAGIC_REG); HOTPLUG_INFO("SLAVE3_MAGIC_NUM:%x\n", SLAVE3_MAGIC_NUM); #endif spm_mtcmos_ctrl_cpu3(STA_POWER_ON, 1); break; default: break; } //smp_cross_call(cpumask_of(cpu)); /* * Now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ spin_unlock(&boot_lock); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb(); if (pen_release == -1) break; udelay(1000); } if (pen_release == -1) { #if 0 //FIXME: update to the right register names pr_emerg("SPM_CA7_CPU0_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_CPU0_PWR_CON)); pr_emerg("SPM_CA7_CPU1_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_CPU1_PWR_CON)); pr_emerg("SPM_CA7_CPU2_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_CPU2_PWR_CON)); pr_emerg("SPM_CA7_CPU3_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_CPU3_PWR_CON)); pr_emerg("SPM_CA7_DBG_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_DBG_PWR_CON)); pr_emerg("SPM_CA7_CPUTOP_PWR_CON: 0x%08x\n", REG_READ(SPM_CA7_CPUTOP_PWR_CON)); pr_emerg("SPM_CA15_CPU0_PWR_CON: 0x%08x\n", REG_READ(SPM_CA15_CPU0_PWR_CON)); pr_emerg("SPM_CA15_CPU1_PWR_CON: 0x%08x\n", REG_READ(SPM_CA15_CPU1_PWR_CON)); pr_emerg("SPM_CA15_CPU2_PWR_CON: 0x%08x\n", REG_READ(SPM_CA15_CPU2_PWR_CON)); pr_emerg("SPM_CA15_CPU3_PWR_CON: 0x%08x\n", REG_READ(SPM_CA15_CPU3_PWR_CON)); pr_emerg("SPM_CA15_CPUTOP_PWR_CON: 0x%08x\n", REG_READ(SPM_CA15_CPUTOP_PWR_CON)); #endif return 0; } else { #if 0 //FIXME: how k2 debug monitor if (is_cpu_type(CA7_TYPEID)) { //write back stage pc on ca7 mt_reg_sync_writel(cpu + 8, DBG_MON_CTL); pr_emerg("CPU%u, DBG_MON_CTL: 0x%08x, DBG_MON_DATA: 0x%08x\n", cpu, *(volatile u32 *)(DBG_MON_CTL), *(volatile u32 *)(DBG_MON_DATA)); } else { //decode statge pc on ca15l mt_reg_sync_writel(3+ (cpu - 4) * 4, CA15L_MON_SEL); pr_emerg("CPU%u, CA15L_MON_SEL: 0x%08x, CA15L_MON: 0x%08x\n", cpu, *(volatile u32 *)(CA15L_MON_SEL), *(volatile u32 *)(CA15L_MON)); } #endif on_each_cpu((smp_call_func_t)dump_stack, NULL, 0); atomic_dec(&hotplug_cpu_count); return -ENOSYS; } }