static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; void __iomem *base; int r; base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return; } mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8173_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); mtk_clk_enable_critical(); }
static int mtk_topckgen_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; void __iomem *base; struct device_node *node = pdev->dev.of_node; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt7629_clk_lock, clk_data); clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static int mtk_infrasys_init(struct platform_device *pdev) { int r, i; struct device_node *node = pdev->dev.of_node; if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) infra_clk_data->clks[i] = ERR_PTR(-ENOENT); } } mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), infra_clk_data); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); if (r) return r; mtk_register_reset_controller(node, 2, 0x30); return 0; }
static int mtk_apmixedsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); if (!clk_data) return -ENOMEM; mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs), clk_data); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static void __init mtk_infrasys_init(struct device_node *node) { struct clk_onecell_data *clk_data; int r; clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); mtk_register_reset_controller(node, 2, 0x30); }
static void __init mtk_infrasys_init_early(struct device_node *node) { int r, i; if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); } mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); }