static int _hsmci_shutdown (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hsmci = (hsmci_ext_t *)ext->handle;
base = hsmci->base;
/* Reset and disable controller */
WRITE32 (MCI_CR, SWRST|PWSDIS);
delay (100);
WRITE32 (MCI_CR, MCIDIS | PWSDIS);
/* Indicate we are done with DMA lib */
dmac_fini(hsmci->dmac_dev);
munmap_device_memory ((void *)pioa_pdsr, 4);
munmap_device_memory ((void *)hsmci->base, cfg->MemLength[0]);
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
munmap_device_io (hsmci->pmc_base, PMC_SIZE);
free(hsmci);
return (MMC_SUCCESS);
}
void omap3_dinit(void *hdl)
{
omap3_spi_t *dev = hdl;
/*
* unmap the register, detach the interrupt
*/
InterruptDetach(dev->iid_spi);
munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN);
/*
* Disable EDMA
*/
if (dev->edma) {
omap3_edma_disablespi(dev);
InterruptDetach(dev->iid_edma);
omap3_edma_detach (dev);
munmap_device_memory((void *)dev->edmavbase, DM6446_EDMA_SIZE);
munmap(dev->dmabuf, OMAP3_SPI_MAXDMALEN);
ConnectDetach(dev->edma_coid);
}
ConnectDetach(dev->coid);
ChannelDestroy(dev->chid);
free(hdl);
}
static err_t gpio_destory(Drive_Gpio *t)
{
Drive_Gpio *cthis = ( Drive_Gpio *)t ;
cthis->disableIrq( cthis);
GPIOModuleDisable( cthis->gpio_vbase);
InterruptDetach( cthis->irq_id);
munmap_device_io( cthis->gpio_vbase, AM335X_GPIO_SIZE);
lw_oopc_delete( cthis);
return EXIT_SUCCESS;
}
void
omap_fini(void *hdl)
{
omap_dev_t *dev = hdl;
out16(dev->regbase + OMAP_I2C_CON, 0);
out16(dev->regbase + OMAP_I2C_IE, 0);
InterruptDetach(dev->iid);
ConnectDetach(dev->coid);
ChannelDestroy(dev->chid);
munmap_device_io (dev->regbase, dev->reglen);
free (hdl);
}
int get_chip_type()
{
uintptr_t port = mmap_device_io( 4, OMAP_CONTROL_ID_CODE);
if (port == MAP_DEVICE_FAILED) {
return 0;
}
uint32_t chip_type = in32(port);
if (chip_type == OMAP5430_CONTROL_ID_CODE || chip_type == OMAP5432_CONTROL_ID_CODE){
rm_l4per_uart1_context = RM_L4PER_UART1_CONTEXT_OMAP5;
rm_l4per_uart2_context = RM_L4PER_UART2_CONTEXT_OMAP5;
rm_l4per_uart3_context = RM_L4PER_UART3_CONTEXT_OMAP5;
rm_l4per_uart4_context = RM_L4PER_UART4_CONTEXT_OMAP5;
}
munmap_device_io(port, 4);
return 1;
}
int main (int argc, char *argv[])
{
int opt = 0, verbose = 0, pin = -1, direction = -1, gpio_module = -1;
int cmd = -1;
extern char *optarg;
// Handle commandline arguments
// -m gpio_module The GPIO module. Can be a value from 1 to 6
// -p pin The GPIO pin you want to set
// -d direction The direction of the GPIO pin. Can be: 0 (=write)|1(=read)
// -c command Action to perform. Can be: set|reset|read
while ((opt = getopt(argc, argv, "m:p:d:c:v")) != -1) {
switch (opt) {
case 'm':
gpio_module = strtol(optarg, NULL, 10);
if (errno != 0) gpio_module = -1;
break;
case 'p':
pin = strtol(optarg, NULL, 10);
if (errno != 0) pin = -1;
break;
case 'd':
direction = strtol(optarg, NULL, 10);
if (errno != 0 || direction > 1) direction = -1;
if (strcmp(optarg, "write") == 0) direction = 0;
else if (strcmp(optarg, "read") == 0) direction = 1;
else direction = -1;
case 'c':
if (strcmp(optarg, "set") == 0) cmd = 0;
else if (strcmp(optarg, "reset") == 0) cmd = 1;
else if (strcmp(optarg, "read") == 0) cmd = 2;
else cmd = -1;
break;
case 'v':
verbose++;
break;
default:
break;
}
}
if (gpio_module != -1 && pin != -1 && direction != -1 && cmd != -1) {
/* enable this thread to execute i/o functions... */
ThreadCtl(_NTO_TCTL_IO, 0);
//ptr = mmap_device_memory( 0, OMAP35XX_GPIO_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, gpio_base[gpio_module - 1]);
ptr = mmap_device_io(OMAP35XX_GPIO_SIZE, gpio_base[gpio_module - 1]);
ctrl_ptr = mmap_device_io(OMAP35XX_GPIO_SIZE, CONTROL_PADCONF_MMC2_CLK);
if ( (void*)ptr == MAP_FAILED ) {
perror( "mmap_device_memory for physical address failed");
exit( EXIT_FAILURE );
}
printf("ctrl_ptr %x\n",in32(ctrl_ptr));
//out32(ctrl_ptr, 0x01040000);
gpio_set_direction(pin, direction);
if (cmd == 0) gpio_set(pin);
if (cmd == 1) gpio_reset(pin);
if (cmd == 2) printf("0x%x\n",gpio_read(direction, pin));
//munmap_device_memory(gpio_base[gpio_module - 1], OMAP35XX_GPIO_SIZE);
munmap_device_io(gpio_base[gpio_module - 1], OMAP35XX_GPIO_SIZE);
munmap_device_io(CONTROL_PADCONF_MMC2_CLK, OMAP35XX_GPIO_SIZE);
return 0;
} else {
printf("Illigal commandline options provided, type 'use %s' on the commandline for usage information:\n", argv[0]);
return -1;
}
}
void *omap3_init(void *hdl, char *options)
{
omap3_spi_t *dev;
uintptr_t base;
int i;
uint32_t reg;
dev = calloc(1, sizeof(omap3_spi_t));
if (dev == NULL)
return NULL;
//Set defaults
dev->pbase = OMAP3_SPI1_BASE;
dev->irq_spi = OMAP3_SPI_SPI1_INTR;
dev->clock = OMAP3_SPI_INPUT_CLOCK;
dev->channel_num = 1;
dev->force = 0;
dev->edmapbase = DM816x_EDMA_BASE;
dev->irq_edma = 0; /* We use interrupt of receive channel */
dev->edma = 0;
dev->num_cs = 1;
dev->cs_delay = 0;
dev->edma_tx_chid = dev->edma_rx_chid = -1;
if (omap3_options(dev, options))
goto fail0;
/*
* Map in SPI registers
*/
if ((base = mmap_device_io(OMAP3_SPI_REGLEN, dev->pbase)) == (uintptr_t)MAP_FAILED)
goto fail0;
dev->vbase = base;
/* Reset the SPI interface
* and wait for the reset to complete
*/
set_port(base + OMAP3_MCSPI_SYS_CONFIG, OMAP3_MCSPI_CONFIG_SOFT_RESET, OMAP3_MCSPI_CONFIG_SOFT_RESET);
while ( !(in32(base + OMAP3_MCSPI_SYS_CONFIG) & 1)) {
nanospin_ns(20);
}
/*Set Master mode -- single channel mode*/
out32((base + OMAP3_MCSPI_MODCTRL_OFFSET), (in32(base + OMAP3_MCSPI_MODCTRL_OFFSET) & OMAP3_MCSPI_MODCTRL_MASTER_SEL)|OMAP3_MCSPI_MODCTRL_MULTI_CH_SEL);
/*
* Calculate all device configuration here
*/
for (i = 0; i < dev->num_cs; i++){ //we have just one device defined in the driver till now....
devctrl[i] = omap3_cfg(dev, &devlist[i].cfg);
if(dev->force){
/* if we need to set the default CSx level to other than defaul low, we need to kick it*/
out32((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14 * i), devctrl[i]|SPI_COMM_TX_RX <<12);
set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, OMAP3_MCSPI_CHANNEL_ENABLE);
/* force CS */
set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, OMAP3_MCSPI_FORCE_MODE_ONE);
delay(1);
/*un force CS */
set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, 0);
set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, 0);
}
}
/*
* Attach SPI interrupt
*/
if (omap3_attach_intr(dev))
goto fail1;
dev->spi.hdl = hdl;
/* Clear the appropriate Interrupts if any*/
reg= in32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET) ;
out32((base + OMAP3_MCSPI_IRQ_STATUS_OFFSET), reg);
if (dev->edma) {
if (omap3_init_edma(dev)) dev->edma=0;
/*
* Attach SDMA interrupt
*/
if (omap3_edma_attach_intr(dev)){
printf("%s(%d): omap3_edma_attach_intr failed\n", __func__, __LINE__);
goto fail2;
}
}
return dev;
fail2:
munmap_device_memory ((void *)dev->edmavbase, DM6446_EDMA_SIZE);
fail1:
munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN);
fail0:
free(dev);
return NULL;
}
int hsmci_init (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci = NULL;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hba->verbosity = 4;
if (!ext->opts) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: missing board-specific options\n");
goto ARGSERR;
}
if ((hsmci = calloc(1, sizeof(hsmci_ext_t))) == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: alloc memory failed\n");
goto ERR;
}
cfg->MemLength[0] = 0x1000;
cfg->NumMemWindows = 1;
cfg->MemBase[0] = cfg->IOPort_Base[0];
base = (uintptr_t)mmap_device_memory(NULL, cfg->MemLength[0],
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, cfg->MemBase[0]);
if (base == (uintptr_t)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
hsmci->clock = 133000000;
hsmci->base = base;
hsmci->hba = hba;
ext->handle = hsmci;
ext->clock = hsmci->clock;
ext->detect = _hsmci_detect;
ext->powerup = _hsmci_powerup;
ext->powerdown = _hsmci_powerdown;
ext->cfg_bus = _hsmci_cfg_bus;
ext->set_clock = _hsmci_clock;
ext->set_blksz = _hsmci_block_size;
ext->interrupt = _hsmci_interrupt;
ext->command = _hsmci_command;
ext->setup_dma = _hsmci_setup_dma;
ext->dma_done = _hsmci_dma_done;
ext->setup_pio = _hsmci_setup_pio;
ext->pio_done = _hsmci_pio_done;
ext->shutdown = _hsmci_shutdown;
/* Parse options */
hsmci->port = -1;
hsmci->blksz = BLK_LENGTH;
hsmci->slot = 0;
/* Hardcode DMAC controller base address according to G45 datasheet
* since this driver is specifically for G45 SoC */
hsmci->dbase = DMAC_BASE;
if (!ext->opts)
goto ARGSERR;
if (hsmci_args(hba, ext->opts) == -1)
goto ARGSERR;
/*
* Set Src/Dst Request peripheral identifier SRC_PER/DST_PER
* handshaking interface # according to Table 41-1 DMA Channel Definition
* According to datasheet Table 35-2, the I/O line of mci0_da0 is pa2.
* According to datasheet Table 35-2, the I/O line of mci1_da0 is pa23.
*/
if (hsmci->port == 0) {
hsmci->dintf = 0;
hsmci->da0_mask = (1<<2);
} else {
hsmci->dintf=13;
hsmci->da0_mask = (1<<23);
}
/* Map G45 PIOA for polling busy signal */
pioa_pdsr = (uint32_t *)mmap_device_memory(NULL, 4,
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, PIOA_PDSR);
if (pioa_pdsr == (uint32_t *)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
if ( (uintptr_t) MAP_FAILED == ( hsmci->pio_base = mmap_device_io( AT91SAM9G45_PIO_SIZE, AT91SAM9G45_PIOD_BASE ) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PIOD_PDSR failed" );
goto ERR;
}
/* Configure CD and WP PIO */
InterruptDisable();
#define CFG_PIO(reg) out32( hsmci->pio_base + (reg), AT91SAM9G45_MCI_PIO_BITS )
CFG_PIO( AT91SAM9G45_PIO_PER ); /* Ensable PIO */
CFG_PIO( AT91SAM9G45_PIO_ODR ); /* Disable output */
CFG_PIO( AT91SAM9G45_PIO_IFDR ); /* Disable glitch input filter */
CFG_PIO( AT91SAM9G45_PIO_CODR ); /* Clear output data */
CFG_PIO( AT91SAM9G45_PIO_IDR ); /* Disable interrupt */
CFG_PIO( AT91SAM9G45_PIO_MDDR ); /* Disable multi-driver */
CFG_PIO( AT91SAM9G45_PIO_PUER ); /* Enable pull-up */
CFG_PIO( AT91SAM9G45_PIO_OWDR ); /* Output write disable */
#undef CFG_PIO
InterruptEnable();
/* Configure capacity of controller */
ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS;
// Use the flag MMC_HCCAP_NOCD_BUSY to inform the MMCSD stack that this hardware has R1B bug
// ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS | MMC_HCCAP_NOCD_BUSY;
/* Disable the controller and soft reset */
WRITE32(MCI_CR, SWRST | PWSDIS);
delay (100);
WRITE32(MCI_CR, MCIDIS | PWSDIS);
/* Disable DMA */
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
/* Enable the controller */
WRITE32(MCI_CR, MCIEN | PWSDIS);
WRITE32(MCI_IDR, 0xffffffff);
/* Set Timeout to Max */
WRITE32(MCI_DTOR, 0x7f);
/* Use the lowest baudrate */
WRITE32 (MCI_MR, 0xff | WRPROOF| RDPROOF);
hsmci->dmac_dev = dmac_init(hsmci);
if (hsmci->dmac_dev == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: dmafuncs init FAILED\n");
goto ERR;
}
hsmci->dmac_dev->io_addr = cfg->MemBase[0] + MCI_FIFO;
hsmci->dmac_dev->blksz = hsmci->blksz;
/* Select slot, set bus to 1 bit */
WRITE32 (MCI_SDCR, hsmci->slot);
if (!cfg->Description[0])
strncpy(cfg->Description, "Atmel HSMCI ", sizeof(cfg->Description));
if ( (uintptr_t) MAP_FAILED == ( hsmci->pmc_base = mmap_device_io(PMC_SIZE, PMC_BASE) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PMC failed" );
goto ERR;
}
return (MMC_SUCCESS);
ARGSERR:
printf("\nImproper board-specific options used. Accepting args: \n");
printf(" port=# The MCI port been used (0 or 1)\n");
printf("NOTE:\n");
printf(" 1. The args are seperated by colon ':'\n");
printf("Example:\n");
printf("at91sam9g45 port 0: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFF80000,irq=11,bs=port=0\n");
printf("at91sam9g45 port 1: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFFD0000,irq=29,bs=port=1\n");
ERR:
if (hsmci) {
munmap_device_memory ((void *)hsmci->base, (uint32_t)cfg->MemLength[0]);
if (hsmci->pio_base)
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
free (hsmci);
}
if (pioa_pdsr != (uint32_t *)MAP_FAILED)
munmap_device_memory ((void *)pioa_pdsr, 4);
return (MMC_FAILURE);
}
void Board_Close(void)
{
munmap_device_io(BIO_SIZE,0x300);
}
//#define CM_PER_GPIO1_CLKCTRL (0xAC) // This register manages the GPIO1 clocks. Section 8.1.2.1.41
//#define CM_PER_GPIO2_CLKCTRL (0xB0) // This register manages the GPIO2 clocks. Section 8.1.2.1.42
//#define CM_PER_GPIO3_CLKCTRL (0xB4) // This register manages the GPIO3 clocks. Section 8.1.2.1.43
//#define CM_PER_GPIO4_CLKCTRL (0xB8) // This register manages the GPIO4 clocks. Section 8.1.2.1.44
void GPIO0ModuleClkConfig(void)
{
static char invo_count = 0;
uintptr_t prcm_base,cm_wkup_regs;
uint32_t val;
if( invo_count) //第二次调用直接退出
return;
invo_count ++;
prcm_base=mmap_device_io(CM_PRCM_SIZE,PRCM_BASE);
cm_wkup_regs=prcm_base+0x400;
/* Writing to MODULEMODE field of CM_WKUP_GPIO0_CLKCTRL register. */
out32(cm_wkup_regs+CM_WKUP_GPIO0_CLKCTRL,CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE);
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_MODULEMODE));
/*
** Writing to OPTFCLKEN_GPIO0_GDBCLK field of CM_WKUP_GPIO0_CLKCTRL
** register.
*/
val=in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL);
val|=CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK;
out32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL,val);
/* Waiting for OPTFCLKEN_GPIO0_GDBCLK field to reflect the written value. */
while(CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK));
/* Verifying if the other bits are set to required settings. */
/*
** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));
/*
** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_L4WKUP_CLKCTRL) &
CM_WKUP_L4WKUP_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
** to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));
/*
** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));
/* Writing to IDLEST field in CM_WKUP_GPIO0_CLKCTRL register. */
while((CM_WKUP_GPIO0_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_GPIO0_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_GPIO0_GDBCLK field in CM_WKUP_GPIO0_CLKCTRL
** register to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK !=
(in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK));
munmap_device_io(prcm_base, CM_PRCM_SIZE);
}