void systemInit(void)
{
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
setupPLL();
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Enable clocks to peripherals and release peripheral reset */
periphInit();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
setupFlash();
/* USER CODE BEGIN (19) */
/* USER CODE END */
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/* USER CODE BEGIN (20) */
/* USER CODE END */
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();
/* USER CODE BEGIN (21) */
/* USER CODE END */
/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)(8U - 1U) & 0xFFFFU);
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
void _c_int00()
{
register uint32_t temp;
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Enable VFP Unit */
_coreEnableVfp_();
/* Initialize Core Registers */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* read the system exception status register */
temp = systemREG1->SYSESR;
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* check for power-on reset condition */
if (temp & 0x8000)
{
/* clear all reset status flags */
systemREG1->SYSESR = 0xFFFF;
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
else if (temp & 0x4000)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (9) */
/* USER CODE END */
}
else if (temp & 0x2000)
{
/* Reset caused due to windowed watchdog violation.
Add user code here to handle watchdog violation */
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
else if (temp & 0x20)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register.
Add user code to handle CPU reset:
check for selftest completion without any error and continue start-up. */
/* USER CODE BEGIN (11) */
/* USER CODE END */
}
else if (temp & 0x10)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (13) */
/* USER CODE END */
}
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* Initialize System */
systemInit();
/* Initialize memory */
// _memoryInit_();
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
// _coreEnableEventBusExport_();
/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
// _coreEnableRamEcc_();
/* Initialize VIM table */
{
uint32_t i;
for (i = 0; i < 90U; i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
| (SYS_FIQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U)
| (SYS_IRQ << 31U);
vimREG->FIRQPR1 = SYS_IRQ
| (SYS_IRQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U)
| (SYS_IRQ << 31U);
vimREG->FIRQPR2 = SYS_IRQ
| (SYS_IRQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U);
/* enable interrupts */
vimREG->REQMASKSET0 = 1U
| (1U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U)
| (0U << 26U)
| (0U << 27U)
| (0U << 28U)
| (0U << 29U)
| (0U << 30U)
| (0U << 31U);
vimREG->REQMASKSET1 = 0U
| (0U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U)
| (0U << 26U)
| (0U << 27U)
| (0U << 28U)
| (0U << 29U)
| (0U << 30U)
| (0U << 31U);
vimREG->REQMASKSET2 = 0U
| (0U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U);
/* initalise copy table */
if ((uint32_t *)&__binit__ != (uint32_t *)0xFFFFFFFFU)
{
extern void copy_in(void *binit);
copy_in((void *)&__binit__);
}
/* initalise the C global variables */
if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
{
uint8_t **tablePtr = (uint8_t **)&__TI_CINIT_Base;
uint8_t **tableLimit = (uint8_t **)&__TI_CINIT_Limit;
while (tablePtr < tableLimit)
{
uint8_t *loadAdr = *tablePtr++;
uint8_t *runAdr = *tablePtr++;
uint8_t idx = *loadAdr++;
handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
(*handler)((const uint8_t *)loadAdr, runAdr);
}
}
/* initalise contructors */
if (__TI_PINIT_Base < __TI_PINIT_Limit)
{
void (**p0)() = (void *)__TI_PINIT_Base;
while ((uint32_t)p0 < __TI_PINIT_Limit)
{
void (*p)() = *p0++;
p();
}
}
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* configure muxed pins */
muxInit();
/* call the application */
main();
exit();
}
/* Requirements : HL_SR471 */
void systemInit(void)
{
uint32 efcCheckStatus;
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
setupPLL();
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheckStatus = efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Enable clocks to peripherals and release peripheral reset */
periphInit();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
if(efcCheckStatus == 0U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
}
else if(efcCheckStatus == 2U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
else
{
selftestFailNotification(EFCCHECK_FAIL2);
}
}
else
{
/* Empty */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
setupFlash();
/* USER CODE BEGIN (21) */
/* USER CODE END */
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/* USER CODE BEGIN (23) */
/* USER CODE END */
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();
/* USER CODE BEGIN (24) */
/* USER CODE END */
/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)(8U - 1U) & 0xFFFFU);
/* USER CODE BEGIN (25) */
/* USER CODE END */
}
/*
* Initialise the GPIO for execution.
*
* 1. Export all the Izmir's GPIOs to sysfs
* 2. Initialise default pin routing on Arduino shield
* 3. TODO reset pin
*
* XXX error reporting
*/
void pinInit(void)
{
int i = 0;
PinDescription *p = NULL;
memset(&ardPin2DescIdx, -1, sizeof(ardPin2DescIdx));
/*
* Export all GPIOs
*/
for (i = 0; i < sizeof_g_APinDescription; i++) {
for (p = &g_APinDescription[i]; p != NULL; p = p->pAlternate) {
/* Skip past any system reserved pin */
if (p->tCurrentType == FN_RESERVED)
continue;
p->iHandle = sysfsGpioExport(p->ulGPIOId, p->sPath, sizeof(p->sPath));
if (p->iHandle < 0){
trace_error("unable to open GPIO %d", p->ulGPIOId);
assert(0);
}
}
/* Fill entry in uint32_t ardPin2PinDescIdx */
if (g_APinDescription[i].ulArduinoId != NONE){
ardPin2DescIdx[g_APinDescription[i].ulArduinoId] = i;
}
}
/* Loop through array and set GPIO to the initial state indicated by the descriptor array */
for (i = 0; i < sizeof_g_APinDescription; i++) {
for (p = &g_APinDescription[i]; p != NULL; p = p->pAlternate) {
if (p->iHandle < 0 && p->tCurrentType != FN_RESERVED) {
trace_error("%s: invalid iHandle for gpio%u",
__func__, p->ulGPIOId);
continue;
}
if (p->tCurrentType & (FN_GPIO_FIXED_INPUT | FN_GPIO_FIXED_OUTPUT | FN_MUX | FN_PULLUP)){
/*
* GPIOs not exported to Arduino header.
* Default drive mode is pullup on.
*/
sysfsGpioSetDrive(p->ulGPIOId, GPIO_DRIVE_PULLUP);
if (p->tCurrentType & (FN_MUX | FN_GPIO_FIXED_OUTPUT | FN_PULLUP)){
// MUX, Fixed output and PULLUPs are all fixed outputs - else it's variable
sysfsGpioDirection(p->ulGPIOId, 1, p->ulFixedState);
}else{
sysfsGpioDirection(p->ulGPIOId, 0, NONE);
}
} else if (p->tCurrentType & FN_GPIO_OPENDRAIN) {
/*
* GPIOs exported on Arduino headers are by
* default input with no pullup
*/
sysfsGpioSetDrive(p->ulGPIOId, GPIO_DRIVE_HIZ);
sysfsGpioDirection(p->ulGPIOId, 0, NONE);
} else {
trace_info("%s gpiolib %d is not a candidate for direction confiugration", __func__, p->ulGPIOId);
}
}
}
/* Now set the inital mux */
muxInit();
/* Finally initialise fast path to GPIO SC */
if (fastGpioSCInit() != 0){
trace_error("Unable to initialise fast GPIO mode!");
}
return;
}
