/*******************************************************************************
* mvEthPhyReset - Reset ethernet Phy.
*
* DESCRIPTION:
* This function resets a given ethernet Phy.
*
* INPUT:
* phyAddr - Phy address.
* timeout - in millisec
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_TIMEOUT - Timeout
*
*******************************************************************************/
MV_STATUS mvEthPhyReset(MV_U32 phyAddr, int timeout)
{
MV_U16 phyRegData;
/* Reset the PHY */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
/* Set bit 15 to reset the PHY */
phyRegData |= ETH_PHY_CTRL_RESET_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
/* Wait untill Reset completed */
while (timeout > 0) {
mvOsSleep(100);
timeout -= 100;
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
if ((phyRegData & ETH_PHY_CTRL_RESET_MASK) == 0)
return MV_OK;
}
return MV_TIMEOUT;
}
MV_VOID mvEth1121PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x1;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
/* Set RGMII delay */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,®);
reg |= (BIT5 | BIT4);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/*******************************************************************************
* mvEthPhyRestartAN - Restart ethernet Phy Auto-Negotiation.
*
* DESCRIPTION:
* This function resets a given ethernet Phy.
*
* INPUT:
* phyAddr - Phy address.
* timeout - in millisec; 0 - no timeout (don't wait)
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_TIMEOUT - Timeout
*
*******************************************************************************/
MV_STATUS mvEthPhyRestartAN(MV_U32 phyAddr, int timeout)
{
MV_U16 phyRegData;
/* Reset the PHY */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
/* Set bit 12 to Enable autonegotiation of the PHY */
phyRegData |= ETH_PHY_CTRL_AN_ENABLE_MASK;
/* Set bit 9 to Restart autonegotiation of the PHY */
phyRegData |= ETH_PHY_CTRL_AN_RESTART_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
if (timeout == 0)
return MV_OK;
/* Wait untill Auotonegotiation completed */
while (timeout > 0) {
mvOsSleep(100);
timeout -= 100;
if (mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &phyRegData) != MV_OK)
return MV_FAIL;
if (phyRegData & ETH_PHY_STATUS_AN_DONE_MASK)
return MV_OK;
}
return MV_TIMEOUT;
}
/*******************************************************************************
* mvEthPhyCheckLink -
*
* DESCRIPTION:
* check link in phy port
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN: MV_TRUE if link is up, MV_FALSE if down
*
*******************************************************************************/
MV_BOOL mvEthPhyCheckLink(MV_U32 phyAddr)
{
MV_U16 val_st, val_ctrl, val_spec_st;
/* read status reg */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_STATUS_REG, &val_st) != MV_OK)
return MV_FALSE;
/* read control reg */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_CTRL_REG, &val_ctrl) != MV_OK)
return MV_FALSE;
/* read special status reg */
if (mvEthPhyRegRead(phyAddr, ETH_PHY_SPEC_STATUS_REG, &val_spec_st) != MV_OK)
return MV_FALSE;
/* Check for PHY exist */
if ((val_ctrl == ETH_PHY_SMI_DATA_MASK) && (val_st & ETH_PHY_SMI_DATA_MASK))
return MV_FALSE;
if (val_ctrl & ETH_PHY_CTRL_AN_ENABLE_MASK) {
if (val_st & ETH_PHY_STATUS_AN_DONE_MASK)
return MV_TRUE;
else
return MV_FALSE;
} else {
if (val_spec_st & ETH_PHY_SPEC_STATUS_LINK_MASK)
return MV_TRUE;
}
return MV_FALSE;
}
MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
void mvEthSwitchRegRead(MV_U32 ethPortNum, MV_U32 phyAddr,
MV_U32 regOffs, MV_U16 *data)
{
MV_U16 reg;
switchMultiChipMode = mvBoardPhyAddrGet(ethPortNum);
if(switchMultiChipMode == 0xdeadbeef) {
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0x2, ®);
if(reg == 0xffff)
switchMultiChipMode = mvBoardPhyAddrGet(ethPortNum);
else
switchMultiChipMode = 0xffffffff;
}
if(switchMultiChipMode == 0xffffffff)
mvEthPhyRegRead(phyAddr, regOffs, data);
else //If Switch is in multichip mode, need to use indirect register access
{
do {
mvEthPhyRegRead(switchMultiChipMode, 0x0, ®);
} while((reg & BIT15)); // Poll till SMIBusy bit is clear
mvEthPhyRegWrite(switchMultiChipMode, 0x0, regOffs | (phyAddr << 5) |
BIT11 | BIT12 | BIT15); // Write command to Switch indirect command register
do {
mvEthPhyRegRead(switchMultiChipMode, 0, ®);
} while((reg & BIT15)); // Poll till SMIBusy bit is clear
mvEthPhyRegRead(switchMultiChipMode, 0x1, data); // Write data to Switch indirect data register
}
}
/*******************************************************************************
* mvEthE6131PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE6131SwitchBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/*Enable Phy power up*/
mvEthPhyRegWrite (0,0,0x9140);
mvEthPhyRegWrite (1,0,0x9140);
mvEthPhyRegWrite (2,0,0x9140);
/*Enable PPU*/
mvEthPhyRegWrite (0x1b,4,0x4080);
/*Enable Phy detection*/
mvEthPhyRegRead (0x13,0,®);
reg &= ~(1<<12);
mvEthPhyRegWrite (0x13,0,reg);
mvOsDelay(100);
mvEthPhyRegWrite (0x13,1,0x33);
switchVlanInit(ethPortNum,
MV_E6131_CPU_PORT,
MV_E6131_MAX_PORTS_NUM,
MV_E6131_PORTS_OFFSET,
MV_E6131_ENABLED_PORTS);
}
MV_VOID mvEth1340PhyBasicInit(void)
{
int i;
MV_U16 reg;
int startAddr, endAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
endAddr = startAddr + 4;
for (i = startAddr; i < endAddr; i++) {
mvEthPhyRegWrite(i, 0x16, 0);
mvEthPhyRegWrite(i, 0x1d, 3);
mvEthPhyRegWrite(i, 0x1e, 2);
mvEthPhyRegWrite(i, 0x1d, 0);
/* Power up the phy */
/* mvEthPhyRegRead(i,ETH_PHY_CTRL_REG, ®); */
/* reg |= ETH_PHY_CTRL_RESET_MASK; */
/* mvEthPhyRegWrite(i,ETH_PHY_CTRL_REG, reg); software reset */
/* Enable QSGMII AN */
/* Set page to 4. */
mvEthPhyRegWrite(i, 0x16, 4);
/* Enable AN */
mvEthPhyRegWrite(i, 0x0, 0x1140);
/* Set page to 0. */
mvEthPhyRegWrite(i, 0x16, 0);
mvEthPhyRegRead(i, ETH_PHY_CTRL_REG, ®);
reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
mvEthPhyRegWrite(i, ETH_PHY_CTRL_REG, reg);
}
}
/*******************************************************************************
* mvEthPhyPrintStatus -
*
* DESCRIPTION:
* print port Speed, Duplex, Auto-negotiation, Link.
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN: 16bit phy register value, or 0xffff on error
*
*******************************************************************************/
MV_STATUS mvEthPhyPrintStatus( MV_U32 phyAddr )
{
MV_U16 val;
/* read control reg */
if( mvEthPhyRegRead( phyAddr, ETH_PHY_CTRL_REG, &val) != MV_OK )
return MV_ERROR;
if( val & ETH_PHY_CTRL_AN_ENABLE_MASK )
mvOsOutput( "Auto negotiation: Enabled\n" );
else
mvOsOutput( "Auto negotiation: Disabled\n" );
/* read specific status reg */
if( mvEthPhyRegRead( phyAddr, ETH_PHY_SPEC_STATUS_REG, &val) != MV_OK )
return MV_ERROR;
switch (val & ETH_PHY_SPEC_STATUS_SPEED_MASK)
{
case ETH_PHY_SPEC_STATUS_SPEED_1000MBPS:
mvOsOutput( "Speed: 1000 Mbps\n" );
break;
case ETH_PHY_SPEC_STATUS_SPEED_100MBPS:
mvOsOutput( "Speed: 100 Mbps\n" );
break;
case ETH_PHY_SPEC_STATUS_SPEED_10MBPS:
mvOsOutput( "Speed: 10 Mbps\n" );
default:
mvOsOutput( "Speed: Uknown\n" );
break;
}
if( val & ETH_PHY_SPEC_STATUS_DUPLEX_MASK )
mvOsOutput( "Duplex: Full\n" );
else
mvOsOutput( "Duplex: Half\n" );
if( val & ETH_PHY_SPEC_STATUS_LINK_MASK )
mvOsOutput("Link: up\n");
else
mvOsOutput("Link: down\n");
return MV_OK;
}
/*******************************************************************************
* mvEthE1111PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1111PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),20,®);
reg |= BIT1 | BIT7;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),20,reg);
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),24,0x4111);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/*******************************************************************************
* mvEthE1011PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1011PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(phyAddr, 20, ®);
reg &= ~(BIT1 | BIT7);
mvEthPhyRegWrite(phyAddr, 20, reg);
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 24, 0x4111);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
void rdPhy(MV_U32 phyAddr, MV_U32 regOffs)
{
MV_U16 data;
MV_STATUS status;
status = mvEthPhyRegRead(phyAddr, regOffs, &data);
if (status == MV_OK)
mvOsPrintf("reg=%d: 0x%04x\n", regOffs, data);
else
mvOsPrintf("Read failed\n");
}
/*******************************************************************************
* mvEthE3016PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE3016PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Leds link and activity*/
mvEthPhyRegRead(phyAddr, 22, ®);
reg &= ~0xf;
reg |= 0xa;
mvEthPhyRegWrite(phyAddr, 22, reg);
/* Set RGMII (RX) delay and copper mode */
mvEthPhyRegRead(phyAddr, 28, ®);
reg &= ~(BIT3 | BIT10 | BIT11);
reg |= (BIT10);
mvEthPhyRegWrite(phyAddr, 28, reg);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
/*******************************************************************************
* mvEthE1111PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1111PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Phy recv and tx delay */
mvEthPhyRegRead(phyAddr, 20, ®);
reg |= BIT1 | BIT7;
mvEthPhyRegWrite(phyAddr, 20, reg);
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 24, 0x4111);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
if (ethphyHalData.boardSpecInit == MV_TRUE)
mvEthPhyRegWrite(phyAddr,
ethphyHalData.specRegOff , ethphyHalData.specData);
}
/*******************************************************************************
* mvEthPhyDisableAN - Disable Phy Auto-Negotiation and set forced Speed and Duplex
*
* DESCRIPTION:
* This function disable AN and set duplex and speed.
*
* INPUT:
* phyAddr - Phy address.
* speed - port speed. 0 - 10 Mbps, 1-100 Mbps, 2 - 1000 Mbps
* duplex - port duplex. 0 - Half duplex, 1 - Full duplex
*
* OUTPUT:
* None.
*
* RETURN: MV_OK - Success
* MV_FAIL - Failure
*
*******************************************************************************/
MV_STATUS mvEthPhyDisableAN(MV_U32 phyAddr, int speed, int duplex)
{
MV_U16 phyRegData;
if(mvEthPhyRegRead (phyAddr, ETH_PHY_CTRL_REG, &phyRegData) != MV_OK)
return MV_FAIL;
switch(speed)
{
case 0: /* 10 Mbps */
phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
case 1: /* 100 Mbps */
phyRegData |= ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData &= ~ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
case 2: /* 1000 Mbps */
phyRegData &= ~ETH_PHY_CTRL_SPEED_LSB_MASK;
phyRegData |= ETH_PHY_CTRL_SPEED_MSB_MASK;
break;
default:
mvOsOutput("Unexpected speed = %d\n", speed);
return MV_FAIL;
}
switch(duplex)
{
case 0: /* half duplex */
phyRegData &= ~ETH_PHY_CTRL_DUPLEX_MASK;
break;
case 1: /* full duplex */
phyRegData |= ETH_PHY_CTRL_DUPLEX_MASK;
break;
default:
mvOsOutput("Unexpected duplex = %d\n", duplex);
}
/* Clear bit 12 to Disable autonegotiation of the PHY */
phyRegData &= ~ETH_PHY_CTRL_AN_ENABLE_MASK;
/* Clear bit 9 to DISABLE, Restart autonegotiation of the PHY */
phyRegData &= ~ETH_PHY_CTRL_AN_RESTART_MASK;
mvEthPhyRegWrite(phyAddr, ETH_PHY_CTRL_REG, phyRegData);
return MV_OK;
}
int mv_eth_tool_read_phy_reg(int phy_addr, u16 page, u16 reg, u16 *val)
{
unsigned long flags;
MV_STATUS status = 0;
spin_lock_irqsave(&mii_lock, flags);
/* setup register address page first */
if (!mvEthPhyRegWrite(phy_addr, MV_ETH_TOOL_PHY_PAGE_ADDR_REG, page)) {
status = mvEthPhyRegRead(phy_addr, reg, val);
}
spin_unlock_irqrestore(&mii_lock, flags);
return status;
}
/*******************************************************************************
* mvEthE1310PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1310PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x11;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
}
/*******************************************************************************
* mvEthE3016PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),22,®);
reg &= ~0xf;
reg |= 0xa;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,reg);
/* Set RGMII (RX) delay and copper mode */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),28,®);
reg &= ~(BIT3 | BIT10 | BIT11);
reg |= (BIT10);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),28,reg);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/******************************************************************************
* mv_eth_tool_read_mdio
* Description:
* MDIO read implementation for kernel core MII calls
* INPUT:
* netdev Network device structure pointer
* addr PHY address
* reg PHY register number (offset)
* OUTPUT
* Register value or -1 on error
*
*******************************************************************************/
int mv_eth_tool_read_mdio(struct net_device *netdev, int addr, int reg)
{
unsigned long flags;
unsigned short value;
MV_STATUS status;
spin_lock_irqsave(&mii_lock, flags);
status = mvEthPhyRegRead(addr, reg, &value);
spin_unlock_irqrestore(&mii_lock, flags);
if (status == MV_OK)
return value;
return -1;
}
/*******************************************************************************
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEth1145PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
mvEthPhyRegWrite(phyAddr, 0x18, ETH_PHY_LED_ACT_LNK_DV);
mvOsDelay(10);
/* Add delay to RGMII Tx and Rx */
mvEthPhyRegRead(phyAddr, 0x14, &value);
mvEthPhyRegWrite(phyAddr, 0x14, (value | BIT1 | BIT7));
mvOsDelay(10);
/* Set Phy TPVL to 0 */
mvEthPhyRegWrite(phyAddr, 0x10, 0x60);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead(phyAddr, 0x00, &value);
mvEthPhyRegWrite(phyAddr, 0x00, (value | BIT15));
mvOsDelay(10);
return;
}
/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1116PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Leds link and activity*/
mvEthPhyRegWrite(phyAddr, 22, 0x3);
mvEthPhyRegRead(phyAddr, 16, ®);
reg &= ~0xf;
reg |= 0x1;
mvEthPhyRegWrite(phyAddr, 16, reg);
mvEthPhyRegWrite(phyAddr, 22, 0x0);
/* Set RGMII delay */
mvEthPhyRegWrite(phyAddr, 22, 2);
mvEthPhyRegRead(phyAddr, 21, ®);
reg |= (BIT5 | BIT4);
mvEthPhyRegWrite(phyAddr, 21, reg);
mvEthPhyRegWrite(phyAddr, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
/*******************************************************************************
* mvEthSgmiiToCopperPhyInit - Initialize Test board 1112 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEthSgmiiToCopperPhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = 0xC;
/* Port 0 phyAdd c */
/* Port 1 phyAdd d */
mvEthPhyRegWrite(phyAddr + port, 22, 3);
mvEthPhyRegWrite(phyAddr + port, 16, 0x103);
mvEthPhyRegWrite(phyAddr + port, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr + port, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr + port, 0, value);
}
static GT_BOOL mv_switch_mii_read(GT_QD_DEV *dev, unsigned int phy, unsigned int reg, unsigned int *data)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&switch_lock, flags);
status = mvEthPhyRegRead(phy, reg, &tmp);
spin_unlock_irqrestore(&switch_lock, flags);
*data = tmp;
if (status == MV_OK)
return GT_TRUE;
return GT_FALSE;
}
GT_BOOL readMiiWrap(GT_QD_DEV* dev, unsigned int portNumber, unsigned int MIIReg, unsigned int* value)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&switch_lock, flags);
status = mvEthPhyRegRead(portNumber, MIIReg , &tmp);
spin_unlock_irqrestore(&switch_lock, flags);
*value = tmp;
if (status == MV_OK)
return GT_TRUE;
return GT_FALSE;
}
MV_VOID mvEth1540PhyBasicInit(MV_BOOL eeeEnable)
{
MV_U16 reg;
int startAddr;
startAddr = ethphyHalData.quadPhyStartAddr;
/* Identify PHY Revision. */
mvEthPhyRegWrite(startAddr, 0x16, 0xFB);
mvEthPhyRegRead(startAddr, 0x1F, ®);
mvEthPhyRegWrite(startAddr, 0x16, 0x0);
if (reg == 0x100)
mvEth1540Y0PhyBasicInit(eeeEnable);
else
mvEth1540A0PhyBasicInit(eeeEnable);
return;
}
int mv_eth_read_mii(unsigned int portNumber, unsigned int MIIReg, unsigned int* value)
{
unsigned long flags;
unsigned short tmp;
MV_STATUS status;
spin_lock_irqsave(&mii_lock, flags);
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
mvSemaLock(MV_SEMA_SMI);
#endif
status = mvEthPhyRegRead(mvBoardPhyAddrGet(portNumber), MIIReg, &tmp);
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
mvSemaUnlock(MV_SEMA_SMI);
#endif
spin_unlock_irqrestore(&mii_lock, flags);
*value = tmp;
if (status == MV_OK)
return 0;
return -1;
}
MV_VOID mvEthInternalGEPhyBasicInit(MV_U32 phyAddr)
{
MV_U16 value;
if (ethphyHalData.ctrlRevId < 2) {
mvEthPhyRegWrite(phyAddr, 0x16, 0x00FF);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0FD0);
mvEthPhyRegWrite(phyAddr, 0x10, 0x214C);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0000);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2000);
mvEthPhyRegWrite(phyAddr, 0x11, 0x0F16);
mvEthPhyRegWrite(phyAddr, 0x10, 0x2146);
mvEthPhyRegWrite(phyAddr, 0x16, 0x0);
}
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
return;
}
/*******************************************************************************
* mvEthE1112PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* phyAddr - PHY address.
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1112PhyBasicInit(MV_U32 phyAddr)
{
MV_U16 reg;
/* Set phy address */
/*MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));*/
/* Implement PHY errata */
mvEthPhyRegWrite(phyAddr, 22, 2);
mvEthPhyRegWrite(phyAddr, 0, 0x140);
mvEthPhyRegWrite(phyAddr, 0, 0x8140);
mvEthPhyRegWrite(phyAddr, 22, 0);
mvEthPhyRegWrite(phyAddr, 22, 3);
mvEthPhyRegWrite(phyAddr, 16, 0x103);
mvEthPhyRegWrite(phyAddr, 22, 0);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, ®);
reg |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, reg);
}
/*******************************************************************************
* mvEthPhyPower -
*
* DESCRIPTION:
* Do a basic power down/up to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
* enable - MV_TRUE - power up
* MV_FALSE - power down
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
static MV_VOID mvEthPhyPower(MV_U32 ethPortNum, MV_BOOL enable)
{
MV_U16 reg;
if (enable == MV_FALSE)
{
/* Power down command */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg |= BIT3;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to disable the SERDES */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power off LED's */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x88);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
reg |= ETH_PHY_CTRL_RESET_BIT;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
reg |= ETH_PHY_CTRL_POWER_DOWN_BIT;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power down the PHY */
}
else
{
/* Power up command */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2); /* select page 2 */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~BIT3;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg); /* select to enable the SERDES */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0); /* select page 0 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,3); /* Power on LED's */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,0x03);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
reg |= ETH_PHY_CTRL_RESET_BIT;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* software reset */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,®);
reg &= ~ETH_PHY_CTRL_POWER_DOWN_BIT;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),ETH_PHY_CTRL_REG,reg); /* power up the PHY */
}
}
