static void mvPp2PlcrHwDumpTitle(void)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_BASE_PERIOD_REG);
mvOsPrintf("PLCR status: %d policers, period=%d (%s), ",
MV_PP2_PLCR_NUM, regVal & MV_PP2_PLCR_BASE_PERIOD_ALL_MASK,
regVal & MV_PP2_PLCR_ADD_TOKENS_EN_MASK ? "En" : "Dis");
regVal = mvPp2RdReg(MV_PP2_PLCR_EDROP_EN_REG);
mvOsPrintf("edrop=%s, ", regVal & MV_PP2_PLCR_EDROP_EN_MASK ? "En" : "Dis");
regVal = mvPp2RdReg(MV_PP2_PLCR_MIN_PKT_LEN_REG);
mvOsPrintf("min_pkt=%d bytes\n", (regVal & MV_PP2_PLCR_MIN_PKT_LEN_ALL_MASK) >> MV_PP2_PLCR_MIN_PKT_LEN_OFFS);
mvOsPrintf("PLCR: enable period unit type tokens c_size e_size c_tokens e_tokens\n");
}
MV_STATUS mvPp2WolSleep(int port)
{
MV_U32 regVal;
if (mvPp2PortCheck(port))
return MV_BAD_PARAM;
/* Clear cause register and unmask enabled WoL events */
mvPp2WrReg(MV_PP2_WOL_INTR_CAUSE_REG, 0);
regVal = mvPp2RdReg(MV_PP2_WOL_WAKEUP_EN_REG);
mvPp2WrReg(MV_PP2_WOL_INTR_MASK_REG, regVal);
regVal = mvPp2RdReg(MV_PP2_WOL_MODE_REG);
if (regVal & MV_PP2_WOL_IS_SLEEP_MASK) {
mvOsPrintf("WoL is already activated on port #%d\n",
(regVal >> MV_PP2_WOL_SLEEP_PORT_OFFS) & MV_PP2_WOL_SLEEP_PORT_MAX);
return MV_BUSY;
}
void mvPp2PlcrHwRegs(void)
{
int i;
MV_U32 regVal;
mvOsPrintf("\n[PLCR registers: %d policers]\n", MV_PP2_PLCR_NUM);
mvEthRegPrint(MV_PP2_PLCR_ENABLE_REG, "MV_PP2_PLCR_ENABLE_REG");
mvEthRegPrint(MV_PP2_PLCR_BASE_PERIOD_REG, "MV_PP2_PLCR_BASE_PERIOD_REG");
mvEthRegPrint(MV_PP2_PLCR_MIN_PKT_LEN_REG, "MV_PP2_PLCR_MIN_PKT_LEN_REG");
mvEthRegPrint(MV_PP2_PLCR_EDROP_EN_REG, "MV_PP2_PLCR_EDROP_EN_REG");
for (i = 0; i < MV_PP2_PLCR_NUM; i++) {
mvOsPrintf("\n[Policer %d registers]\n", i);
mvPp2WrReg(MV_PP2_PLCR_TABLE_INDEX_REG, i);
mvEthRegPrint(MV_PP2_PLCR_COMMIT_TOKENS_REG, "MV_PP2_PLCR_COMMIT_TOKENS_REG");
mvEthRegPrint(MV_PP2_PLCR_EXCESS_TOKENS_REG, "MV_PP2_PLCR_EXCESS_TOKENS_REG");
mvEthRegPrint(MV_PP2_PLCR_BUCKET_SIZE_REG, "MV_PP2_PLCR_BUCKET_SIZE_REG");
mvEthRegPrint(MV_PP2_PLCR_TOKEN_CFG_REG, "MV_PP2_PLCR_TOKEN_CFG_REG");
}
mvOsPrintf("\nEarly Drop Thresholds for SW and HW forwarding\n");
for (i = 0; i < MV_PP2_PLCR_EDROP_THRESH_NUM; i += 2) {
mvEthRegPrint2(MV_PP2_PLCR_EDROP_CPU_TR_REG(i), "MV_PP2_PLCR_EDROP_CPU_TR_REG", i);
mvEthRegPrint2(MV_PP2_PLCR_EDROP_HWF_TR_REG(i), "MV_PP2_PLCR_EDROP_HWF_TR_REG", i);
}
mvOsPrintf("\nPer RXQ: Non zero early drop thresholds\n");
for (i = 0; i < MV_ETH_RXQ_TOTAL_NUM; i++) {
mvPp2WrReg(MV_PP2_PLCR_EDROP_RXQ_REG, i);
regVal = mvPp2RdReg(MV_PP2_PLCR_EDROP_RXQ_TR_REG);
if (regVal != 0)
mvOsPrintf(" %-32s: 0x%x = 0x%08x\n", "MV_PP2_PLCR_EDROP_RXQ_TR_REG", MV_PP2_PLCR_EDROP_RXQ_TR_REG, regVal);
}
mvOsPrintf("\nPer TXQ: Non zero Early Drop Thresholds\n");
for (i = 0; i < MV_PP2_TXQ_TOTAL_NUM; i++) {
mvPp2WrReg(MV_PP2_PLCR_EDROP_TXQ_REG, i);
regVal = mvPp2RdReg(MV_PP2_PLCR_EDROP_TXQ_TR_REG);
if (regVal != 0)
mvOsPrintf(" %-32s: 0x%x = 0x%08x\n", "MV_PP2_PLCR_EDROP_TXQ_TR_REG", MV_PP2_PLCR_EDROP_TXQ_TR_REG, regVal);
}
}
MV_STATUS mvPp2PlcrHwHwfThreshSet(int idx, int threshold)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_EDROP_HWF_TR_REG(idx));
regVal &= ~MV_PP2_PLCR_EDROP_TR_ALL_MASK(idx);
regVal |= MV_PP2_PLCR_EDROP_TR_MASK(idx, threshold);
mvPp2WrReg(MV_PP2_PLCR_EDROP_HWF_TR_REG(idx), regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwMinPktLen(int bytes)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_MIN_PKT_LEN_REG);
regVal &= ~MV_PP2_PLCR_MIN_PKT_LEN_ALL_MASK;
regVal |= MV_PP2_PLCR_MIN_PKT_LEN_MASK(bytes);
mvPp2WrReg(MV_PP2_PLCR_MIN_PKT_LEN_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwBasePeriodSet(int period)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_BASE_PERIOD_REG);
regVal &= ~MV_PP2_PLCR_BASE_PERIOD_ALL_MASK;
regVal |= MV_PP2_PLCR_BASE_PERIOD_MASK(period);
mvPp2WrReg(MV_PP2_PLCR_BASE_PERIOD_REG, regVal);
return MV_OK;
}
static void mvPp2PlcrHwDump(int plcr)
{
int units, type, tokens;
MV_U32 regVal;
mvPp2WrReg(MV_PP2_PLCR_TABLE_INDEX_REG, plcr);
mvOsPrintf("%3d: ", plcr);
regVal = mvPp2RdReg(MV_PP2_PLCR_ENABLE_REG);
mvOsPrintf("%4s", MV_BIT_CHECK(regVal, plcr) ? "Yes" : "No");
regVal = mvPp2RdReg(MV_PP2_PLCR_BASE_PERIOD_REG);
mvOsPrintf(" %6d", regVal & MV_PP2_PLCR_BASE_PERIOD_ALL_MASK);
regVal = mvPp2RdReg(MV_PP2_PLCR_TOKEN_CFG_REG);
units = regVal & MV_PP2_PLCR_TOKEN_UNIT_MASK;
type = (regVal & MV_PP2_PLCR_TOKEN_TYPE_ALL_MASK) >> MV_PP2_PLCR_TOKEN_TYPE_OFFS;
tokens = (regVal & MV_PP2_PLCR_TOKEN_VALUE_ALL_MASK) >> MV_PP2_PLCR_TOKEN_VALUE_OFFS;
mvOsPrintf(" %5s %2d %5d", units ? "pkts" : "bytes", type, tokens);
regVal = mvPp2RdReg(MV_PP2_PLCR_BUCKET_SIZE_REG);
mvOsPrintf(" %04x %04x",
(regVal & MV_PP2_PLCR_COMMIT_SIZE_ALL_MASK) >> MV_PP2_PLCR_COMMIT_SIZE_OFFS,
(regVal & MV_PP2_PLCR_EXCESS_SIZE_ALL_MASK) >> MV_PP2_PLCR_EXCESS_SIZE_OFFS);
regVal = mvPp2RdReg(MV_PP2_PLCR_COMMIT_TOKENS_REG);
mvOsPrintf(" %08x", regVal);
regVal = mvPp2RdReg(MV_PP2_PLCR_EXCESS_TOKENS_REG);
mvOsPrintf(" %08x", regVal);
mvOsPrintf("\n");
}
MV_STATUS mvPp2PlcrHwTokenValue(int plcr, int value)
{
MV_U32 regVal;
mvPp2WrReg(MV_PP2_PLCR_TABLE_INDEX_REG, plcr);
regVal = mvPp2RdReg(MV_PP2_PLCR_TOKEN_CFG_REG);
regVal &= ~MV_PP2_PLCR_TOKEN_VALUE_ALL_MASK;
regVal |= MV_PP2_PLCR_TOKEN_VALUE_MASK(value);
mvPp2WrReg(MV_PP2_PLCR_TOKEN_CFG_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwEarlyDropSet(int enable)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_EDROP_EN_REG);
if (enable)
regVal |= MV_PP2_PLCR_EDROP_EN_MASK;
else
regVal &= ~MV_PP2_PLCR_EDROP_EN_MASK;
mvPp2WrReg(MV_PP2_PLCR_EDROP_EN_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwEnable(int plcr, int enable)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_ENABLE_REG);
if (enable)
regVal |= MV_PP2_PLCR_EN_MASK(plcr);
else
regVal &= ~MV_PP2_PLCR_EN_MASK(plcr);
mvPp2WrReg(MV_PP2_PLCR_ENABLE_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwBaseRateGenEnable(int enable)
{
MV_U32 regVal;
regVal = mvPp2RdReg(MV_PP2_PLCR_BASE_PERIOD_REG);
if (enable)
regVal |= MV_PP2_PLCR_ADD_TOKENS_EN_MASK;
else
regVal &= ~MV_PP2_PLCR_ADD_TOKENS_EN_MASK;
mvPp2WrReg(MV_PP2_PLCR_BASE_PERIOD_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwColorModeSet(int plcr, int enable)
{
MV_U32 regVal;
mvPp2WrReg(MV_PP2_PLCR_TABLE_INDEX_REG, plcr);
regVal = mvPp2RdReg(MV_PP2_PLCR_TOKEN_CFG_REG);
if (enable)
regVal |= MV_PP2_PLCR_COLOR_MODE_MASK;
else
regVal &= ~MV_PP2_PLCR_COLOR_MODE_MASK;
mvPp2WrReg(MV_PP2_PLCR_TOKEN_CFG_REG, regVal);
return MV_OK;
}
MV_STATUS mvPp2PlcrHwTokenConfig(int plcr, int unit, int type)
{
MV_U32 regVal;
mvPp2WrReg(MV_PP2_PLCR_TABLE_INDEX_REG, plcr);
regVal = mvPp2RdReg(MV_PP2_PLCR_TOKEN_CFG_REG);
if (unit)
regVal |= MV_PP2_PLCR_TOKEN_UNIT_MASK;
else
regVal &= ~MV_PP2_PLCR_TOKEN_UNIT_MASK;
regVal &= ~MV_PP2_PLCR_TOKEN_TYPE_ALL_MASK;
regVal |= MV_PP2_PLCR_TOKEN_TYPE_MASK(type);
mvPp2WrReg(MV_PP2_PLCR_TOKEN_CFG_REG, regVal);
return MV_OK;
}
