int board_late_init(void) { const char *e; #ifdef CONFIG_FEC_MXC struct iomuxc_mux_ctl *muxctl; u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); /* * fec pin init is generic */ mx25_fec_init_pins(); /* * Set up LAN-RESET and FEC_RX_ERR * * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20 * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 */ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); /* assert PHY reset (low) */ gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0); udelay(5000); /* deassert PHY reset */ gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1); udelay(5000); #endif e = getenv("gs_base_board"); if (e != NULL) { if (strcmp(e, "G283") == 0) { int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29)); if (key) { /* Switch on both LEDs to inidcate boot mode */ gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0); gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0); setenv("preboot", "run gs_slow_boot"); } else setenv("preboot", "run gs_fast_boot"); } } return 0; }
void tx25_fec_init(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; u32 val; u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; debug("tx25_fec_init\n"); /* * fec pin init is generic */ mx25_fec_init_pins(); /* * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. * * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13 * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11 */ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; writel(gpio_mux_mode, &muxctl->pad_d13); writel(gpio_mux_mode, &muxctl->pad_d11); writel(0x0, &padctl->pad_d13); writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); writel(val, &gpio4->gpio_dr); val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); writel(val, &gpio4->gpio_dir); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ val = readl(&gpio4->gpio_dr) | 1 << 9; writel(val, &gpio4->gpio_dr); mdelay(10); /* * Setup some strapping pins that are latched by the PHY * as reset goes high. * * Set PHY mode to 111 * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 * mode2 is tied high so nothing to do * * Turn on RMII mode * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode */ /* * save three current mux modes and set each to gpio mode */ saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0); saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1); saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv); writel(gpio_mux_mode, &muxctl->pad_fec_rdata0); writel(gpio_mux_mode, &muxctl->pad_fec_rdata1); writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv); /* * set each to 1 and make each an output */ val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); writel(val, &gpio3->gpio_dr); val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); writel(val, &gpio3->gpio_dir); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ val = readl(&gpio4->gpio_dr) | 1 << 7; writel(val, &gpio4->gpio_dr); writel(val, &gpio4->gpio_dr); mdelay(5); /* * set FEC pins back */ writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0); writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1); writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv); }