void __init mxc_timer_init(const char *clk_timer) { timer_clk = clk_get(NULL, clk_timer); if (!timer_clk) { printk(KERN_ERR"Cannot determine timer clock. Giving up.\n"); return; } clk_enable(timer_clk); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, TIMER_BASE + MXC_TCTL); __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */ __raw_writel(TCTL_FRR | /* free running */ TCTL_VAL | /* set clocksource and arch specific bits */ TCTL_TEN, /* start the timer */ TIMER_BASE + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(); mxc_clockevent_init(); /* Make irqs happen */ setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); }
void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { uint32_t tctl_val; clk_enable(timer_clk); timer_base = base; /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { uint32_t tctl_val; clk_enable(timer_clk); timer_base = base; __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); if (cpu_is_mx3() || cpu_is_mx25()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); setup_irq(irq, &mxc_timer_irq); }
static void __init _mxc_timer_init(int irq, struct clk *clk_per, struct clk *clk_ipg) { uint32_t tctl_val; if (IS_ERR(clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; } if (!IS_ERR(clk_ipg)) clk_prepare_enable(clk_ipg); clk_prepare_enable(clk_per); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sll() || cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx7d()) { /* 24 / 8 = 3 MHz */ __raw_writel(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } } else { tctl_val |= V2_TCTL_CLK_PER; } } else { tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(clk_per); mxc_clockevent_init(clk_per); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, unsigned long phys, int irq) { uint32_t tctl_val; clk_enable(timer_clk); timer_base = base; /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); #ifdef CONFIG_IPIPE __ipipe_mach_timerint = irq; __ipipe_mach_ticks_per_jiffy = (clk_get_rate(timer_clk) + HZ/2) / HZ; tsc_info.freq = clk_get_rate(timer_clk); mxc_min_delay = ((__ipipe_cpu_freq + 500000) / 1000000) ?: 1; if (timer_is_v1()) { tsc_info.u.counter_paddr = phys + MX1_2_TCN; tsc_info.counter_vaddr =(unsigned long)(phys + MX1_2_TCN); } else { tsc_info.u.counter_paddr = phys + V2_TCN; tsc_info.counter_vaddr = (unsigned long)(timer_base + V2_TCN); } __ipipe_tsc_register(&tsc_info); #endif /* CONFIG_IPIPE */ }
void __init mxc_timer_init(struct clk *timer_clk) { uint32_t tctl_val; int irq; clk_enable(timer_clk); if (cpu_is_mx1()) { #ifdef CONFIG_ARCH_MX1 timer_base = IO_ADDRESS(TIM1_BASE_ADDR); irq = TIM1_INT; #endif } else if (cpu_is_mx2()) { #ifdef CONFIG_ARCH_MX2 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT1; #endif } else if (cpu_is_mx3()) { #ifdef CONFIG_ARCH_MX3 timer_base = IO_ADDRESS(GPT1_BASE_ADDR); irq = MXC_INT_GPT; #endif } else BUG(); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (cpu_is_mx3()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) { uint32_t tctl_val; u32 reg; clk_enable(timer_clk); timer_base = base; /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { if (cpu_is_mx5() || cpu_is_mx6sl() || mx6q_revision() == IMX_CHIP_REVISION_1_0) tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else { tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; if (!cpu_is_mx6q()) { reg = __raw_readl(timer_base + MXC_TPRER); reg |= (V2_TPRER_PRE24M_DIV8 << V2_TPRER_PRE24M_OFFSET); __raw_writel(reg, timer_base + MXC_TPRER); /* Enable the 24MHz input clock. */ tctl_val |= V2_TCTL_ENABLE24M; } } } else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
void __init mxc_timer_init(struct clk *timer_clk) { clk_enable(timer_clk); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, TIMER_BASE + MXC_TCTL); __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */ __raw_writel(TCTL_FRR | /* free running */ TCTL_VAL | /* set clocksource and arch specific bits */ TCTL_TEN, /* start the timer */ TIMER_BASE + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); }
static void __init _mxc_timer_init(int irq, struct clk *clk_per, struct clk *clk_ipg) { uint32_t tctl_val; if (IS_ERR(clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; } if (!IS_ERR(clk_ipg)) clk_prepare_enable(clk_ipg); clk_prepare_enable(clk_per); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(clk_per); mxc_clockevent_init(clk_per); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }