static int lcdif_init(struct mxc_dispdrv_handle *disp,
struct mxc_dispdrv_setting *setting)
{
int ret, i;
struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
struct fsl_mxc_lcd_platform_data *plat_data
= lcdif->pdev->dev.platform_data;
struct fb_videomode *modedb = lcdif_modedb;
int modedb_sz = lcdif_modedb_sz;
/* use platform defined ipu/di */
setting->dev_id = plat_data->ipu_id;
setting->disp_id = plat_data->disp_id;
ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
modedb, modedb_sz, NULL, setting->default_bpp);
if (!ret) {
fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
setting->if_fmt = plat_data->default_ifmt;
}
INIT_LIST_HEAD(&setting->fbi->modelist);
for (i = 0; i < modedb_sz; i++) {
struct fb_videomode m;
fb_var_to_videomode(&m, &setting->fbi->var);
if (fb_mode_is_equal(&m, &modedb[i])) {
fb_add_videomode(&modedb[i],
&setting->fbi->modelist);
break;
}
}
return ret;
}
static int ldb_disp_setup(struct mxc_dispdrv_handle *disp, struct fb_info *fbi)
{
uint32_t reg, val;
uint32_t pixel_clk, rounded_pixel_clk;
struct clk *ldb_clk_parent;
struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
int setting_idx, di;
setting_idx = find_ldb_setting(ldb, fbi);
if (setting_idx < 0)
return setting_idx;
di = ldb->setting[setting_idx].di;
/* restore channel mode setting */
val = readl(ldb->control_reg);
val |= ldb->setting[setting_idx].ch_val;
writel(val, ldb->control_reg);
dev_dbg(&ldb->pdev->dev, "LDB setup, control reg:0x%x\n",
readl(ldb->control_reg));
/* vsync setup */
reg = readl(ldb->control_reg);
if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) {
if (di == 0)
reg = (reg & ~LDB_DI0_VS_POL_MASK)
| LDB_DI0_VS_POL_ACT_HIGH;
else
reg = (reg & ~LDB_DI1_VS_POL_MASK)
| LDB_DI1_VS_POL_ACT_HIGH;
} else {
if (di == 0)
reg = (reg & ~LDB_DI0_VS_POL_MASK)
| LDB_DI0_VS_POL_ACT_LOW;
else
reg = (reg & ~LDB_DI1_VS_POL_MASK)
| LDB_DI1_VS_POL_ACT_LOW;
}
writel(reg, ldb->control_reg);
/* clk setup */
if (ldb->setting[setting_idx].clk_en)
clk_disable(ldb->setting[setting_idx].ldb_di_clk);
pixel_clk = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL;
ldb_clk_parent = clk_get_parent(ldb->setting[setting_idx].ldb_di_clk);
if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1))
clk_set_rate(ldb_clk_parent, pixel_clk * 7 / 2);
else
clk_set_rate(ldb_clk_parent, pixel_clk * 7);
rounded_pixel_clk = clk_round_rate(ldb->setting[setting_idx].ldb_di_clk,
pixel_clk);
clk_set_rate(ldb->setting[setting_idx].ldb_di_clk, rounded_pixel_clk);
clk_enable(ldb->setting[setting_idx].ldb_di_clk);
if (!ldb->setting[setting_idx].clk_en)
ldb->setting[setting_idx].clk_en = true;
return 0;
}
static void ldb_disp_deinit(struct mxc_dispdrv_handle *disp)
{
struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
int i;
writel(0, ldb->control_reg);
for (i = 0; i < 2; i++) {
clk_disable(ldb->setting[i].ldb_di_clk);
clk_put(ldb->setting[i].ldb_di_clk);
}
fb_unregister_client(&ldb->nb);
iounmap(ldb->reg);
}
static void adv739x_disp_deinit(struct mxc_dispdrv_handle *disp)
{
struct adv739x_data *adv739x = mxc_dispdrv_getdata(disp);
struct fsl_mxc_lcd_platform_data *plat = adv739x->client->dev.platform_data;
if (adv739x->client->irq)
free_irq(adv739x->client->irq, adv739x);
fb_unregister_client(&adv739x->nb);
adv739x_poweroff(adv739x);
/* Release pins */
if (plat->put_pins)
plat->put_pins();
platform_device_unregister(adv739x->pdev);
}
static int ldb_disp_init(struct mxc_dispdrv_handle *disp,
struct mxc_dispdrv_setting *setting)
{
int ret = 0, i;
struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data;
struct resource *res;
uint32_t base_addr;
uint32_t reg, setting_idx;
uint32_t ch_mask = 0, ch_val = 0;
uint32_t ipu_id, disp_id;
/* if input format not valid, make RGB666 as default*/
if (!valid_mode(setting->if_fmt)) {
dev_warn(&ldb->pdev->dev, "Input pixel format not valid"
" use default RGB666\n");
setting->if_fmt = IPU_PIX_FMT_RGB666;
}
if (!ldb->inited) {
char di_clk[] = "ipu1_di0_clk";
char ldb_clk[] = "ldb_di0_clk";
int lvds_channel = 0;
setting_idx = 0;
res = platform_get_resource(ldb->pdev, IORESOURCE_MEM, 0);
if (IS_ERR(res))
return -ENOMEM;
base_addr = res->start;
ldb->reg = ioremap(base_addr, res->end - res->start + 1);
ldb->control_reg = ldb->reg + 2;
ldb->gpr3_reg = ldb->reg + 3;
ldb->lvds_bg_reg = regulator_get(&ldb->pdev->dev, plat_data->lvds_bg_reg);
if (!IS_ERR(ldb->lvds_bg_reg)) {
regulator_set_voltage(ldb->lvds_bg_reg, 2500000, 2500000);
regulator_enable(ldb->lvds_bg_reg);
}
/* ipu selected by platform data setting */
setting->dev_id = plat_data->ipu_id;
reg = readl(ldb->control_reg);
/* refrence resistor select */
reg &= ~LDB_BGREF_RMODE_MASK;
if (plat_data->ext_ref)
reg |= LDB_BGREF_RMODE_EXT;
else
reg |= LDB_BGREF_RMODE_INT;
/* TODO: now only use SPWG data mapping for both channel */
reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK);
reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG;
/* channel mode setting */
reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
reg &= ~(LDB_DATA_WIDTH_CH0_MASK | LDB_DATA_WIDTH_CH1_MASK);
if (bits_per_pixel(setting->if_fmt) == 24)
reg |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24;
else
reg |= LDB_DATA_WIDTH_CH0_18 | LDB_DATA_WIDTH_CH1_18;
if (g_ldb_mode)
ldb->mode = g_ldb_mode;
else
ldb->mode = plat_data->mode;
if ((ldb->mode == LDB_SIN0) || (ldb->mode == LDB_SIN1)) {
ret = ldb->mode - LDB_SIN0;
if (plat_data->disp_id != ret) {
dev_warn(&ldb->pdev->dev,
"change IPU DI%d to IPU DI%d for LDB "
"channel%d.\n",
plat_data->disp_id, ret, ret);
plat_data->disp_id = ret;
}
} else if (((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))
&& (cpu_is_mx6q() || cpu_is_mx6dl())) {
if (plat_data->disp_id == plat_data->sec_disp_id) {
dev_err(&ldb->pdev->dev,
"For LVDS separate mode,"
"two DIs should be different!\n");
return -EINVAL;
}
if (((!plat_data->disp_id) && (ldb->mode == LDB_SEP1))
|| ((plat_data->disp_id) &&
(ldb->mode == LDB_SEP0))) {
dev_dbg(&ldb->pdev->dev,
"LVDS separate mode:"
"swap DI configuration!\n");
ipu_id = plat_data->ipu_id;
disp_id = plat_data->disp_id;
plat_data->ipu_id = plat_data->sec_ipu_id;
plat_data->disp_id = plat_data->sec_disp_id;
plat_data->sec_ipu_id = ipu_id;
plat_data->sec_disp_id = disp_id;
}
}
if (ldb->mode == LDB_SPL_DI0) {
reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0
| LDB_CH1_MODE_EN_TO_DI0;
setting->disp_id = 0;
} else if (ldb->mode == LDB_SPL_DI1) {
reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1
| LDB_CH1_MODE_EN_TO_DI1;
setting->disp_id = 1;
} else if (ldb->mode == LDB_DUL_DI0) {
reg &= ~LDB_SPLIT_MODE_EN;
reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0;
setting->disp_id = 0;
} else if (ldb->mode == LDB_DUL_DI1) {
reg &= ~LDB_SPLIT_MODE_EN;
reg |= LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1;
setting->disp_id = 1;
} else if (ldb->mode == LDB_SIN0) {
reg &= ~LDB_SPLIT_MODE_EN;
setting->disp_id = plat_data->disp_id;
if (setting->disp_id == 0)
reg |= LDB_CH0_MODE_EN_TO_DI0;
else
reg |= LDB_CH0_MODE_EN_TO_DI1;
ch_mask = LDB_CH0_MODE_MASK;
ch_val = reg & LDB_CH0_MODE_MASK;
} else if (ldb->mode == LDB_SIN1) {
reg &= ~LDB_SPLIT_MODE_EN;
setting->disp_id = plat_data->disp_id;
if (setting->disp_id == 0)
reg |= LDB_CH1_MODE_EN_TO_DI0;
else
reg |= LDB_CH1_MODE_EN_TO_DI1;
ch_mask = LDB_CH1_MODE_MASK;
ch_val = reg & LDB_CH1_MODE_MASK;
} else { /* separate mode*/
setting->disp_id = plat_data->disp_id;
/* first output is LVDS0 or LVDS1 */
if (ldb->mode == LDB_SEP0)
lvds_channel = 0;
else
lvds_channel = 1;
reg &= ~LDB_SPLIT_MODE_EN;
if ((lvds_channel == 0) && (setting->disp_id == 0))
reg |= LDB_CH0_MODE_EN_TO_DI0;
else if ((lvds_channel == 0) && (setting->disp_id == 1))
reg |= LDB_CH0_MODE_EN_TO_DI1;
else if ((lvds_channel == 1) && (setting->disp_id == 0))
reg |= LDB_CH1_MODE_EN_TO_DI0;
else
reg |= LDB_CH1_MODE_EN_TO_DI1;
ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
LDB_CH0_MODE_MASK;
ch_val = reg & ch_mask;
if (bits_per_pixel(setting->if_fmt) == 24) {
if (lvds_channel == 0)
reg &= ~LDB_DATA_WIDTH_CH1_24;
else
reg &= ~LDB_DATA_WIDTH_CH0_24;
} else {
if (lvds_channel == 0)
reg &= ~LDB_DATA_WIDTH_CH1_18;
else
reg &= ~LDB_DATA_WIDTH_CH0_18;
}
}
writel(reg, ldb->control_reg);
if (ldb->mode < LDB_SIN0) {
ch_mask = LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK;
ch_val = reg & (LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
}
/* clock setting */
if ((cpu_is_mx6q() || cpu_is_mx6dl()) &&
((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1)))
ldb_clk[6] += lvds_channel;
else
ldb_clk[6] += setting->disp_id;
ldb->setting[setting_idx].ldb_di_clk = clk_get(&ldb->pdev->dev,
ldb_clk);
if (IS_ERR(ldb->setting[setting_idx].ldb_di_clk)) {
dev_err(&ldb->pdev->dev, "get ldb clk0 failed\n");
iounmap(ldb->reg);
return PTR_ERR(ldb->setting[setting_idx].ldb_di_clk);
}
di_clk[3] += setting->dev_id;
di_clk[7] += setting->disp_id;
ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev,
di_clk);
if (IS_ERR(ldb->setting[setting_idx].di_clk)) {
dev_err(&ldb->pdev->dev, "get di clk0 failed\n");
iounmap(ldb->reg);
return PTR_ERR(ldb->setting[setting_idx].di_clk);
}
dev_dbg(&ldb->pdev->dev, "ldb_clk to di clk: %s -> %s\n", ldb_clk, di_clk);
/* fb notifier for clk setting */
ldb->nb.notifier_call = ldb_fb_event,
ret = fb_register_client(&ldb->nb);
if (ret < 0) {
iounmap(ldb->reg);
return ret;
}
ldb->inited = true;
} else { /* second time for separate mode */
char di_clk[] = "ipu1_di0_clk";
char ldb_clk[] = "ldb_di0_clk";
int lvds_channel;
if ((ldb->mode == LDB_SPL_DI0) ||
(ldb->mode == LDB_SPL_DI1) ||
(ldb->mode == LDB_DUL_DI0) ||
(ldb->mode == LDB_DUL_DI1) ||
(ldb->mode == LDB_SIN0) ||
(ldb->mode == LDB_SIN1)) {
dev_err(&ldb->pdev->dev, "for second ldb disp"
"ldb mode should in separate mode\n");
return -EINVAL;
}
setting_idx = 1;
if (cpu_is_mx6q() || cpu_is_mx6dl()) {
setting->dev_id = plat_data->sec_ipu_id;
setting->disp_id = plat_data->sec_disp_id;
} else {
setting->dev_id = plat_data->ipu_id;
setting->disp_id = !plat_data->disp_id;
}
if (setting->disp_id == ldb->setting[0].di) {
dev_err(&ldb->pdev->dev, "Err: for second ldb disp in"
"separate mode, DI should be different!\n");
return -EINVAL;
}
/* second output is LVDS0 or LVDS1 */
if (ldb->mode == LDB_SEP0)
lvds_channel = 1;
else
lvds_channel = 0;
reg = readl(ldb->control_reg);
if ((lvds_channel == 0) && (setting->disp_id == 0))
reg |= LDB_CH0_MODE_EN_TO_DI0;
else if ((lvds_channel == 0) && (setting->disp_id == 1))
reg |= LDB_CH0_MODE_EN_TO_DI1;
else if ((lvds_channel == 1) && (setting->disp_id == 0))
reg |= LDB_CH1_MODE_EN_TO_DI0;
else
reg |= LDB_CH1_MODE_EN_TO_DI1;
ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
LDB_CH0_MODE_MASK;
ch_val = reg & ch_mask;
if (bits_per_pixel(setting->if_fmt) == 24) {
if (lvds_channel == 0)
reg |= LDB_DATA_WIDTH_CH0_24;
else
reg |= LDB_DATA_WIDTH_CH1_24;
} else {
if (lvds_channel == 0)
reg |= LDB_DATA_WIDTH_CH0_18;
else
reg |= LDB_DATA_WIDTH_CH1_18;
}
writel(reg, ldb->control_reg);
/* clock setting */
if (cpu_is_mx6q() || cpu_is_mx6dl())
ldb_clk[6] += lvds_channel;
else
ldb_clk[6] += setting->disp_id;
ldb->setting[setting_idx].ldb_di_clk = clk_get(&ldb->pdev->dev,
ldb_clk);
if (IS_ERR(ldb->setting[setting_idx].ldb_di_clk)) {
dev_err(&ldb->pdev->dev, "get ldb clk1 failed\n");
return PTR_ERR(ldb->setting[setting_idx].ldb_di_clk);
}
di_clk[3] += setting->dev_id;
di_clk[7] += setting->disp_id;
ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev,
di_clk);
if (IS_ERR(ldb->setting[setting_idx].di_clk)) {
dev_err(&ldb->pdev->dev, "get di clk1 failed\n");
return PTR_ERR(ldb->setting[setting_idx].di_clk);
}
dev_dbg(&ldb->pdev->dev, "ldb_clk to di clk: %s -> %s\n", ldb_clk, di_clk);
}
ldb->setting[setting_idx].ch_mask = ch_mask;
ldb->setting[setting_idx].ch_val = ch_val;
if (cpu_is_mx6q() || cpu_is_mx6dl())
ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb);
/*
* ldb_di0_clk -> ipux_di0_clk
* ldb_di1_clk -> ipux_di1_clk
*/
clk_set_parent(ldb->setting[setting_idx].di_clk,
ldb->setting[setting_idx].ldb_di_clk);
/* must use spec video mode defined by driver */
ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
ldb_modedb, ldb_modedb_sz, NULL, setting->default_bpp);
if (ret != 1)
fb_videomode_to_var(&setting->fbi->var, &ldb_modedb[0]);
INIT_LIST_HEAD(&setting->fbi->modelist);
for (i = 0; i < ldb_modedb_sz; i++) {
struct fb_videomode m;
fb_var_to_videomode(&m, &setting->fbi->var);
if (fb_mode_is_equal(&m, &ldb_modedb[i])) {
fb_add_videomode(&ldb_modedb[i],
&setting->fbi->modelist);
break;
}
}
/* save current ldb setting for fb notifier */
ldb->setting[setting_idx].active = true;
ldb->setting[setting_idx].ipu = setting->dev_id;
ldb->setting[setting_idx].di = setting->disp_id;
return ret;
}
static int lcdif_init(struct mxc_dispdrv_handle *disp,
struct mxc_dispdrv_setting *setting)
{
int ret, i;
struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
struct fsl_mxc_lcd_platform_data *plat_data
= lcdif->pdev->dev.platform_data;
struct fb_videomode *modedb = lcdif_modedb;
int modedb_sz = lcdif_modedb_sz;
struct fsl_video_timing *custom_timing;
/* use platform defined ipu/di */
setting->dev_id = plat_data->ipu_id;
setting->disp_id = plat_data->disp_id;
if (plat_data->lcd0_timing != NULL) {
custom_timing = plat_data->lcd0_timing;
lcdif_modedb[0].pixclock =
PICOS2KHZ(custom_timing->pixclock);
lcdif_modedb[0].xres =
custom_timing->hres;
lcdif_modedb[0].left_margin =
custom_timing->hfp;
lcdif_modedb[0].right_margin =
custom_timing->hbp;
lcdif_modedb[0].hsync_len =
custom_timing->hsw;
lcdif_modedb[0].yres =
custom_timing->vres;
lcdif_modedb[0].upper_margin =
custom_timing->vfp;
lcdif_modedb[0].lower_margin =
custom_timing->vbp;
lcdif_modedb[0].vsync_len =
custom_timing->vsw;
}
if (plat_data->lcd1_timing != NULL) {
custom_timing = plat_data->lcd1_timing;
lcdif_modedb[1].pixclock =
PICOS2KHZ(custom_timing->pixclock);
lcdif_modedb[1].xres =
custom_timing->hres;
lcdif_modedb[1].left_margin =
custom_timing->hfp;
lcdif_modedb[1].right_margin =
custom_timing->hbp;
lcdif_modedb[1].hsync_len =
custom_timing->hsw;
lcdif_modedb[1].yres =
custom_timing->vres;
lcdif_modedb[1].upper_margin =
custom_timing->vfp;
lcdif_modedb[1].lower_margin =
custom_timing->vbp;
lcdif_modedb[1].vsync_len =
custom_timing->vsw;
}
ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
modedb, modedb_sz, NULL, setting->default_bpp);
if (!ret) {
fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
setting->if_fmt = plat_data->default_ifmt;
}
INIT_LIST_HEAD(&setting->fbi->modelist);
for (i = 0; i < modedb_sz; i++) {
struct fb_videomode m;
fb_var_to_videomode(&m, &setting->fbi->var);
if (fb_mode_is_equal(&m, &modedb[i])) {
fb_add_videomode(&modedb[i],
&setting->fbi->modelist);
break;
}
}
return ret;
}
static int adv739x_disp_init(struct mxc_dispdrv_handle *disp,
struct mxc_dispdrv_setting *setting)
{
int ret = 0, i;
struct adv739x_data *adv739x = mxc_dispdrv_getdata(disp);
struct fsl_mxc_lcd_platform_data *plat = adv739x->client->dev.platform_data;
struct fb_videomode *modedb = adv739x_modedb;
int modedb_sz = adv739x_modedb_sz;
static bool inited = false;
if (inited)
return -EBUSY;
inited = true;
setting->dev_id = plat->ipu_id;
setting->disp_id = plat->disp_id;
{
struct clk *di_parent;
struct clk *di;
char di_clk[] = "ipu1_di0_clk";
di_clk[3] += setting->dev_id;
di_clk[7] += setting->disp_id;
di = clk_get(NULL, di_clk);
if (IS_ERR(di)) {
pr_err("%s: clock %s not found\n", __func__, di_clk);
}
di_parent = clk_get(NULL, "pll3_pfd_540M");
if (IS_ERR(di_parent)) {
pr_err("%s: clock pll3_pfd_540M not found\n", __func__);
}
clk_set_parent(di, di_parent);
clk_set_rate(di, 540000000/5);
clk_enable(di_parent);
}
ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
modedb, modedb_sz, NULL, setting->default_bpp);
if (!ret) {
fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
setting->if_fmt = plat->default_ifmt;
adv739x->ifmt = plat->default_ifmt;
}
INIT_LIST_HEAD(&setting->fbi->modelist);
for (i = 0; i < modedb_sz; i++) {
fb_add_videomode(&modedb[i],
&setting->fbi->modelist);
}
adv739x->fbi = setting->fbi;
adv739x->enabled = 0;
adv739x->cur_mode = ADV739X_MODE_NTSC; //default mode
adv739x->pdev = platform_device_register_simple("mxc_adv739x", 0, NULL, 0);
if (IS_ERR(adv739x->pdev)) {
dev_err(&adv739x->client->dev,
"Unable to register adv739x as a platform device\n");
ret = PTR_ERR(adv739x->pdev);
goto register_pltdev_failed;
}
/* Claim pins */
if (plat->get_pins)
if (!plat->get_pins()) {
ret = -EACCES;
goto get_pins_failed;
}
adv739x->nb.notifier_call = adv739x_fb_event;
ret = fb_register_client(&adv739x->nb);
if (ret < 0)
goto reg_fbclient_failed;
return ret;
reg_fbclient_failed:
get_pins_failed:
platform_device_unregister(adv739x->pdev);
register_pltdev_failed:
return ret;
}
