static void mxs_power_init_dcdc_4p2_source(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; if (!(readl(&power_regs->hw_power_dcdc4p2) & POWER_DCDC4P2_ENABLE_DCDC)) { hang(); } mxs_enable_4p2_dcdc_input(1); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC); writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_clr); writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_set); } }
/** * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source * * This function configures the DC-DC converter to be supplied from the 4P2 * linear regulator. */ static void mxs_power_init_dcdc_4p2_source(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; debug("SPL: Switching DC-DC converters to 4P2\n"); if (!(readl(&power_regs->hw_power_dcdc4p2) & POWER_DCDC4P2_ENABLE_DCDC)) { debug("SPL: Already switched - aborting\n"); hang(); } mxs_enable_4p2_dcdc_input(1); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC); writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_clr); writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_set); } }
/** * mxs_power_init_4p2_regulator() - Start the 4P2 regulator * * This function enables the 4P2 regulator and switches the DC-DC converter * to use the 4P2 input. */ static void mxs_power_init_4p2_regulator(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, tmp2; debug("SPL: Enabling 4P2 regulator\n"); setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, &power_regs->hw_power_5vctrl_clr); clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); /* Power up the 4p2 rail and logic/control */ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_clr); /* * Start charging up the 4p2 capacitor. We ramp of this charge * gradually to avoid large inrush current from the 5V cable which can * cause transients/problems */ debug("SPL: Charging 4P2 capacitor\n"); mxs_enable_4p2_dcdc_input(0); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { /* * If we arrived here, we were unable to recover from mx23 chip * errata 5837. 4P2 is disabled and sufficient battery power is * not present. Exiting to not enable DCDC power during 5V * connected state. */ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC); writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_set); debug("SPL: Unable to recover from mx23 errata 5837\n"); hang(); } /* * Here we set the 4p2 brownout level to something very close to 4.2V. * We then check the brownout status. If the brownout status is false, * the voltage is already close to the target voltage of 4.2V so we * can go ahead and set the 4P2 current limit to our max target limit. * If the brownout status is true, we need to ramp us the current limit * so that we don't cause large inrush current issues. We step up the * current limit until the brownout status is false or until we've * reached our maximum defined 4p2 current limit. */ debug("SPL: Setting 4P2 brownout level\n"); clrsetbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK, 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { setbits_le32(&power_regs->hw_power_5vctrl, 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } else { tmp = (readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; while (tmp < 0x3f) { if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { tmp = readl(&power_regs->hw_power_5vctrl); tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; early_delay(100); writel(tmp, &power_regs->hw_power_5vctrl); break; } else { tmp++; tmp2 = readl(&power_regs->hw_power_5vctrl); tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; tmp2 |= tmp << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; writel(tmp2, &power_regs->hw_power_5vctrl); early_delay(100); } } } clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); }