void tia_calibration(int via_fpga, int fd, unsigned short addr, unsigned char *pval)
{
unsigned char reg1DB, reg1DC, reg1DD, reg1DE, reg1DF;
unsigned int reg1EB, reg1EC, reg1E6, Cbbf, R2346, temp;
float BBBW_MHz, CTIA_fF;//需确定
BBBW_MHz = 9;
reg1EB = Ad9361ReadReg(via_fpga, fd, 0x1eb);
reg1EC = Ad9361ReadReg(via_fpga, fd, 0x1ec);
reg1E6 = Ad9361ReadReg(via_fpga, fd, 0x1e6);
if(BBBW_MHz > 28)
{
BBBW_MHz = 28;
}
else if(BBBW_MHz < 0.2)
{
BBBW_MHz = 0.2;
}
Cbbf = (reg1EB * 160) + (reg1EC * 10) + 140;//fF
R2346 = 18300 * (reg1E6 & 7);
CTIA_fF = (Cbbf * R2346 * 0.56) / 3500;
if(myceil(BBBW_MHz) <= 3)
{
reg1DB = 0xE0;
}
else if(myceil(BBBW_MHz) > 3 && myceil(BBBW_MHz) <= 10)
{
reg1DB = 0x60;
}
else if(myceil(BBBW_MHz) > 10)
{
reg1DB = 0x20;
}
if(CTIA_fF > 2920)
{
reg1DC = 0x40;
reg1DE = 0x40;
temp = min(127, myround((CTIA_fF - 400) / 320));
reg1DD = temp;
reg1DF = temp;
}
else
{
temp = myround((CTIA_fF - 400) / 40) + 0x40;
reg1DC = temp;
reg1DE = temp;
reg1DD = 0;
reg1DF = 0;
}
if(addr == 0x1DB)
*pval = reg1DB;
else if(addr == 0x1DC)
*pval = reg1DC;
else if(addr == 0x1DD)
*pval = reg1DD;
else if(addr == 0x1DE)
*pval = reg1DE;
else if(addr == 0x1DF)
*pval = reg1DF;
}
void DecScheduleRAT(int nu, int slot) {
int i;
int fuNu;
ScheduledSlotPtr head, p0, p1;
int op_type = DFG[nu]->op;
int resource_nu = DFG[nu]->opResourceNu;
fuNu = (GetOpSym(op_type) == 'm' || GetOpSym(op_type) == 'r') ?
FU[op_type] : myceil(FU[op_type], minII);
// find the FU and slot to which the operation is assigned
for (i = 0; i < fuNu; i++) {
p1 = p0 = SRAT[op_type][i].head;
while (p0 != NULL) {
if (p0->slot == slot && resource_nu == i + 1) {
(SRAT[op_type][i]).slotNu--;
myprintf("Decrement %s%d at slot %d\n", opSymTable(op_type), i, slot);
// delete the list elem
p1->next = p0->next;
if ((SRAT[op_type][i]).slotNu == 0) (SRAT[op_type][i]).head = NULL;
free(p0);
return;
}
p1 = p0;
p0 = p0 -> next;
}
}
}
