void stm32f4x7EthEventHandler(NetInterface *interface) { error_t error; size_t length; //Packet received? if(ETH->DMASR & ETH_DMASR_RS) { //Clear interrupt flag ETH->DMASR = ETH_DMASR_RS; //Process all pending packets do { //Read incoming packet error = stm32f4x7EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable DMA interrupts ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE; }
void a2fxxxm3EthEventHandler(NetInterface *interface) { error_t error; size_t length; //Packet received? if(MAC->CSR5 & CSR5_RI_MASK) { //Clear interrupt flag MAC->CSR5 = CSR5_RI_MASK; //Process all pending packets do { //Read incoming packet error = a2fxxxm3EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable Ethernet interrupts MAC->CSR7 |= CSR7_NIE_MASK | CSR7_RIE_MASK | CSR7_TIE_MASK; }
void xmc4700EthEventHandler(NetInterface *interface) { error_t error; size_t length; //Packet received? if(ETH0->STATUS & ETH_STATUS_RI_Msk) { //Clear interrupt flag ETH0->STATUS = ETH_STATUS_RI_Msk; //Process all pending packets do { //Read incoming packet error = xmc4700EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable DMA interrupts ETH0->INTERRUPT_ENABLE |= ETH_INTERRUPT_ENABLE_NIE_Msk | ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk; }
void rza1EthEventHandler(NetInterface *interface) { error_t error; size_t length; bool_t linkStateChange; //PHY event is pending? if(interface->phyEvent) { //Acknowledge the event by clearing the flag interface->phyEvent = FALSE; //Handle PHY specific events linkStateChange = interface->phyDriver->eventHandler(interface); //Check whether the link state has changed? if(linkStateChange) { //Set duplex mode for proper operation if(interface->linkState) { //Half-duplex or full-duplex mode? if(interface->fullDuplex) ETHER.ECMR0 |= ETH_ECMR0_DM; else ETHER.ECMR0 &= ~ETH_ECMR0_DM; } //Process link state change event nicNotifyLinkChange(interface); } } //Packet received? if(ETHER.EESR0 & ETHER_EESR0_FR) { //Clear FR interrupt flag ETHER.EESR0 = ETHER_EESR0_FR; //Process all pending packets do { //Read incoming packet error = rza1EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable EDMAC interrupts ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP; }
void wilc1000AppEthEvent(uint8_t msgType, void *msg, void *ctrlBuf) { size_t n; tstrM2mIpCtrlBuf *ctrl; //Debug message TRACE_DEBUG("WILC1000 RX event callback\r\n"); //Point to the control buffer ctrl = (tstrM2mIpCtrlBuf *) ctrlBuf; //Check message type if(msgType == M2M_WIFI_RESP_ETHERNET_RX_PACKET) { //Debug message TRACE_DEBUG(" M2M_WIFI_RESP_ETHERNET_RX_PACKET\r\n"); //Retrieve the length of the packet n = ctrl->u16DataSize; //CRC is not included in the transfer... rxBuffer[n++] = 0xCC; rxBuffer[n++] = 0xCC; rxBuffer[n++] = 0xCC; rxBuffer[n++] = 0xCC; //Check interface identifier if(ctrl->u8IfcId == INTERFACE_1) { //Pass the packet to the upper layer (STA mode) if(wilc1000StaInterface != NULL) nicProcessPacket(wilc1000StaInterface, rxBuffer, n); } else if(ctrl->u8IfcId == INTERFACE_2) { //Pass the packet to the upper layer (AP mode) if(wilc1000ApInterface != NULL) nicProcessPacket(wilc1000ApInterface, rxBuffer, n); } } }
void samv71EthEventHandler(NetInterface *interface) { uint32_t rsr; uint_t length; bool_t linkStateChange; //Read receive status rsr = GMAC->GMAC_RSR; //PHY event is pending? if(interface->phyEvent) { //Acknowledge the event by clearing the flag interface->phyEvent = FALSE; //Handle PHY specific events linkStateChange = interface->phyDriver->eventHandler(interface); //Check whether the link state has changed? if(linkStateChange) { //Set speed and duplex mode for proper operation if(interface->linkState) { //Read network configuration register uint32_t config = GMAC->GMAC_NCFGR; //10BASE-T or 100BASE-TX operation mode? if(interface->speed100) config |= GMAC_NCFGR_SPD; else config &= ~GMAC_NCFGR_SPD; //Half-duplex or full-duplex mode? if(interface->fullDuplex) config |= GMAC_NCFGR_FD; else config &= ~GMAC_NCFGR_FD; //Write configuration value back to NCFGR register GMAC->GMAC_NCFGR = config; } //Process link state change event nicNotifyLinkChange(interface); } } //Packet received? if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA)) { //Only clear RSR flags that are currently set GMAC->GMAC_RSR = rsr; //Process all the pending packets while(1) { //Check whether a packet has been received length = samv71EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE); //No packet is pending in the receive buffer? if(!length) break; //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } } }
void rx63nEthEventHandler(NetInterface *interface) { error_t error; size_t length; bool_t linkStateChange; //PHY event is pending? if(interface->phyEvent) { //Acknowledge the event by clearing the flag interface->phyEvent = FALSE; //Handle PHY specific events linkStateChange = interface->phyDriver->eventHandler(interface); //Check whether the link state has changed? if(linkStateChange) { //Set speed and duplex mode for proper operation if(interface->linkState) { //10BASE-T or 100BASE-TX operation mode? if(interface->speed100) ETHERC.ECMR.BIT.RTM = 1; else ETHERC.ECMR.BIT.RTM = 0; //Half-duplex or full-duplex mode? if(interface->fullDuplex) ETHERC.ECMR.BIT.DM = 1; else ETHERC.ECMR.BIT.DM = 0; } //Process link state change event nicNotifyLinkChange(interface); } } //Packet received? if(EDMAC.EESR.LONG & EDMAC_EESR_FR) { //Clear FR interrupt flag EDMAC.EESR.LONG = EDMAC_EESR_FR; //Process all pending packets do { //Read incoming packet error = rx63nEthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable EDMAC interrupts EDMAC.EESIPR.BIT.TWBIP = 1; EDMAC.EESIPR.BIT.FRIP = 1; }
void m2sxxxEthEventHandler(NetInterface *interface) { error_t error; size_t length; bool_t linkStateChange; uint32_t temp; //PHY event is pending? if(interface->phyEvent) { //Acknowledge the event by clearing the flag interface->phyEvent = FALSE; //Handle PHY specific events linkStateChange = interface->phyDriver->eventHandler(interface); //Check whether the link state has changed? if(linkStateChange) { //Set speed and duplex mode for proper operation if(interface->linkState) { //10BASE-T or 100BASE-TX operation mode? if(interface->speed100) { //The link operates at 100 Mbps temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED; SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_100MBPS; //Configure the RMII module with the current operating speed MAC->INTERFACE_CTRL |= INTERFACE_CTRL_SPEED; //Use nibble mode temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE; MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE; } else { //The link operates at 10 Mbps temp = SYSREG->MAC_CR & ~MAC_CR_ETH_LINE_SPEED; SYSREG->MAC_CR = temp | MAC_CR_ETH_LINE_SPEED_10MBPS; //Configure the RMII module with the current operating speed MAC->INTERFACE_CTRL &= ~INTERFACE_CTRL_SPEED; //Use nibble mode temp = MAC->CFG2 & ~CFG2_INTERFACE_MODE; MAC->CFG2 = temp | CFG2_INTERFACE_MODE_NIBBLE; } //Half-duplex or full-duplex mode? if(interface->fullDuplex) { //Configure MAC to operate in full-duplex mode MAC->CFG2 |= CFG2_FULL_DUPLEX; MAC->FIFO_CFG5 &= ~FIFO_CFG5_CFGHDPLX; } else { //Configure MAC to operate in half-duplex mode MAC->CFG2 &= ~CFG2_FULL_DUPLEX; MAC->FIFO_CFG5 |= FIFO_CFG5_CFGHDPLX; } } //Process link state change event nicNotifyLinkChange(interface); } } //Packet received? if(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED) { //Process all the pending packets while(MAC->DMA_RX_STATUS & DMA_RX_STATUS_RX_PKT_RECEIVED) { //Clear RX interrupt flag MAC->DMA_RX_STATUS = DMA_RX_STATUS_RX_PKT_RECEIVED; //Read incoming packet error = m2sxxxEthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } } } //Re-enable Ethernet interrupts MAC->DMA_IRQ_MASK = DMA_IRQ_MASK_RX_PKT_RECEIVED | DMA_IRQ_MASK_TX_PKT_SENT; }
void dm9000EventHandler(NetInterface *interface) { error_t error; uint8_t status; size_t length; //Read interrupt status register status = dm9000ReadReg(DM9000_REG_ISR); //Check whether the link status has changed? if(status & ISR_LNKCHG) { //Clear interrupt flag dm9000WriteReg(DM9000_REG_ISR, ISR_LNKCHG); //Read network status register status = dm9000ReadReg(DM9000_REG_NSR); //Check link state if(status & NSR_LINKST) { //Link is up interface->linkState = TRUE; //Get current speed interface->speed100 = (status & NSR_SPEED) ? FALSE : TRUE; //Read network control register status = dm9000ReadReg(DM9000_REG_NCR); //Determine the new duplex mode interface->fullDuplex = (status & NCR_FDX) ? TRUE : FALSE; //Display link state TRACE_INFO("Link is up (%s)...\r\n", interface->name); //Display actual speed and duplex mode TRACE_INFO("%s %s\r\n", interface->speed100 ? "100BASE-TX" : "10BASE-T", interface->fullDuplex ? "Full-Duplex" : "Half-Duplex"); } else { //Link is down interface->linkState = FALSE; //Display link state TRACE_INFO("Link is down (%s)...\r\n", interface->name); } //Process link state change event nicNotifyLinkChange(interface); } //Check whether a packet has been received? if(status & ISR_PR) { //Clear interrupt flag dm9000WriteReg(DM9000_REG_ISR, ISR_PR); //Process all pending packets do { //Read incoming packet error = dm9000ReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable LNKCHGI and PRI interrupts dm9000WriteReg(DM9000_REG_IMR, IMR_PAR | IMR_LNKCHGI | IMR_PTI | IMR_PRI); }
void tm4c129EthEventHandler(NetInterface *interface) { error_t error; size_t length; uint32_t status; //PHY interrupt? if(EMAC0_EPHYRIS_R & EMAC_EPHYRIS_INT) { //Clear PHY interrupt flag EMAC0_EPHYMISC_R = EMAC_EPHYMISC_INT; //Read PHY interrupt status register status = tm4c129EthReadPhyReg(EPHY_MISR1); //Check whether the link state has changed? if(status & EPHY_MISR1_LINKSTAT) { //Read BMSR register status = tm4c129EthReadPhyReg(EPHY_BMSR); //Check whether link is up? if(status & EPHY_BMSR_LINKSTAT) { //Read PHY status register status = tm4c129EthReadPhyReg(EPHY_STS); //Check current speed if(status & EPHY_STS_SPEED) { //10BASE-T operation interface->linkSpeed = NIC_LINK_SPEED_10MBPS; //Update MAC configuration EMAC0_CFG_R &= ~EMAC_CFG_FES; } else { //100BASE-TX operation interface->linkSpeed = NIC_LINK_SPEED_100MBPS; //Update MAC configuration EMAC0_CFG_R |= EMAC_CFG_FES; } //Check current duplex mode if(status & EPHY_STS_DUPLEX) { //Full-Duplex mode interface->duplexMode = NIC_FULL_DUPLEX_MODE; //Update MAC configuration EMAC0_CFG_R |= EMAC_CFG_DUPM; } else { //Half-Duplex mode interface->duplexMode = NIC_HALF_DUPLEX_MODE; //Update MAC configuration EMAC0_CFG_R &= ~EMAC_CFG_DUPM; } //Update link state interface->linkState = TRUE; } else { //Update link state interface->linkState = FALSE; } //Process link state change event nicNotifyLinkChange(interface); } } //Packet received? if(EMAC0_DMARIS_R & EMAC_DMARIS_RI) { //Clear interrupt flag EMAC0_DMARIS_R = EMAC_DMARIS_RI; //Process all pending packets do { //Read incoming packet error = tm4c129EthReceivePacket(interface, interface->ethFrame, ETH_MAX_FRAME_SIZE, &length); //Check whether a valid packet has been received if(!error) { //Pass the packet to the upper layer nicProcessPacket(interface, interface->ethFrame, length); } //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); } //Re-enable DMA interrupts EMAC0_DMAIM_R |= EMAC_DMAIM_NIE | EMAC_DMAIM_RIE | EMAC_DMAIM_TIE; //Re-enable PHY interrupts EMAC0_EPHYIM_R |= EMAC_EPHYIM_INT; }