void
trapinit(void)
{
/*
* Special traps.
* Syscall() is called directly without going through trap().
*/
trapenable(VectorBPT, debugbpt, 0, "debugpt");
trapenable(VectorPF, fault386, 0, "fault386");
trapenable(Vector2F, doublefault, 0, "doublefault");
trapenable(Vector15, unexpected, 0, "unexpected");
nmienable();
addarchfile("irqalloc", 0444, irqallocread, nil);
trapinited = 1;
}
void
trapinit(void)
{
/*
* Need to set BPT interrupt gate - here or in vsvminit?
*/
/*
* Special traps.
* Syscall() is called directly without going through trap().
*/
trapenable(VectorBPT, debugbpt, 0, "#BP");
trapenable(VectorPF, faultamd64, 0, "#PF");
trapenable(Vector2F, doublefault, 0, "#DF");
intrenable(IdtIPI, expected, 0, BUSUNKNOWN, "#IPI");
trapenable(Vector15, unexpected, 0, "#15");
nmienable();
addarchfile("irqalloc", 0444, irqallocread, nil);
}
/*
* All traps come here. It is slower to have all traps call trap()
* rather than directly vectoring the handler. However, this avoids a
* lot of code duplication and possible bugs. The only exception is
* VectorSYSCALL.
* Trap is called with interrupts disabled via interrupt-gates.
*/
void
trap(Ureg* ureg)
{
int clockintr, vno, user;
// cache the previous vno to see what might be causing
// trouble
static int lastvno;
vno = ureg->type;
uint64_t gsbase = rdmsr(GSbase);
//if (sce > scx) iprint("====================");
if (vno == 8) {
iprint("Lstar is %p\n", (void *)rdmsr(Lstar));
iprint("GSbase is %p\n", (void *)gsbase);
iprint("ire %d irx %d sce %d scx %d lastvno %d\n",
ire, irx, sce, scx, lastvno);
iprint("irxe %d \n",
irxe);
die("8");
}
lastvno = vno;
if (gsbase < 1ULL<<63)
die("bogus gsbase");
Mach *m = machp();
char buf[ERRMAX];
Vctl *ctl, *v;
if (0 && m && m->externup && m->externup->pid == 6) {
//iprint("type %x\n", ureg->type);
if (ureg->type != 0x49)
die("6\n");
}
m->perf.intrts = perfticks();
user = userureg(ureg);
if(user && (m->nixtype == NIXTC)){
m->externup->dbgreg = ureg;
cycles(&m->externup->kentry);
}
clockintr = 0;
//_pmcupdate(m);
if(ctl = vctl[vno]){
if(ctl->isintr){
m->intr++;
if(vno >= VectorPIC && vno != VectorSYSCALL)
m->lastintr = ctl->irq;
}else
if(m->externup)
m->externup->nqtrap++;
if(ctl->isr)
ctl->isr(vno);
for(v = ctl; v != nil; v = v->next){
if(v->f)
v->f(ureg, v->a);
}
if(ctl->eoi)
ctl->eoi(vno);
intrtime(vno);
if(ctl->isintr){
if(ctl->irq == IrqCLOCK || ctl->irq == IrqTIMER)
clockintr = 1;
if(m->externup && !clockintr)
preempted();
}
}
else if(vno < nelem(excname) && user){
spllo();
snprint(buf, sizeof buf, "sys: trap: %s", excname[vno]);
postnote(m->externup, 1, buf, NDebug);
}
else if(vno >= VectorPIC && vno != VectorSYSCALL){
/*
* An unknown interrupt.
* Check for a default IRQ7. This can happen when
* the IRQ input goes away before the acknowledge.
* In this case, a 'default IRQ7' is generated, but
* the corresponding bit in the ISR isn't set.
* In fact, just ignore all such interrupts.
*/
/* clear the interrupt */
i8259isr(vno);
iprint("cpu%d: spurious interrupt %d, last %d\n",
m->machno, vno, m->lastintr);
intrtime(vno);
if(user)
kexit(ureg);
return;
}
else{
if(vno == VectorNMI){
nmienable();
if(m->machno != 0){
iprint("cpu%d: PC %#llux\n",
m->machno, ureg->ip);
for(;;);
}
}
dumpregs(ureg);
if(!user){
ureg->sp = PTR2UINT(&ureg->sp);
dumpstackwithureg(ureg);
}
if(vno < nelem(excname))
panic("%s", excname[vno]);
panic("unknown trap/intr: %d\n", vno);
}
splhi();
/* delaysched set because we held a lock or because our quantum ended */
if(m->externup && m->externup->delaysched && clockintr){
if(0)
if(user && m->externup->ac == nil && m->externup->nqtrap == 0 && m->externup->nqsyscall == 0){
if(!waserror()){
m->externup->ac = getac(m->externup, -1);
poperror();
runacore();
return;
}
}
sched();
splhi();
}
if(user){
if(m->externup && m->externup->procctl || m->externup->nnote)
notify(ureg);
kexit(ureg);
}
}
/*
* All traps come here. It is slower to have all traps call trap()
* rather than directly vectoring the handler. However, this avoids a
* lot of code duplication and possible bugs. The only exception is
* VectorSYSCALL.
* Trap is called with interrupts disabled via interrupt-gates.
*/
void
trap(Ureg* ureg)
{
int clockintr, vno, user;
// cache the previous vno to see what might be causing
// trouble
vno = ureg->type;
uint64_t gsbase = rdmsr(GSbase);
//if (sce > scx) iprint("====================");
lastvno = vno;
if (gsbase < 1ULL<<63)
die("bogus gsbase");
Proc *up = externup();
char buf[ERRMAX];
Vctl *ctl, *v;
machp()->perf.intrts = perfticks();
user = userureg(ureg);
if(user && (machp()->NIX.nixtype == NIXTC)){
up->dbgreg = ureg;
cycles(&up->kentry);
}
clockintr = 0;
//_pmcupdate(machp());
if((ctl = vctl[vno]) != nil){
if(ctl->isintr){
machp()->intr++;
if(vno >= VectorPIC && vno != VectorSYSCALL)
machp()->lastintr = ctl->Vkey.irq;
}else
if(up)
up->nqtrap++;
if(ctl->isr){
ctl->isr(vno);
if(islo())print("trap %d: isr %p enabled interrupts\n", vno, ctl->isr);
}
for(v = ctl; v != nil; v = v->next){
if(v->f){
v->f(ureg, v->a);
if(islo())print("trap %d: ctlf %p enabled interrupts\n", vno, v->f);
}
}
if(ctl->eoi){
ctl->eoi(vno);
if(islo())print("trap %d: eoi %p enabled interrupts\n", vno, ctl->eoi);
}
intrtime(vno);
if(ctl->isintr){
if(ctl->Vkey.irq == IrqCLOCK || ctl->Vkey.irq == IrqTIMER)
clockintr = 1;
if (ctl->Vkey.irq == IrqTIMER)
oprof_alarm_handler(ureg);
if(up && !clockintr)
preempted();
}
}
else if(vno < nelem(excname) && user){
spllo();
snprint(buf, sizeof buf, "sys: trap: %s", excname[vno]);
postnote(up, 1, buf, NDebug);
}
else if(vno >= VectorPIC && vno != VectorSYSCALL){
/*
* An unknown interrupt.
* Check for a default IRQ7. This can happen when
* the IRQ input goes away before the acknowledge.
* In this case, a 'default IRQ7' is generated, but
* the corresponding bit in the ISR isn't set.
* In fact, just ignore all such interrupts.
*/
/* clear the interrupt */
i8259isr(vno);
iprint("cpu%d: spurious interrupt %d, last %d\n",
machp()->machno, vno, machp()->lastintr);
intrtime(vno);
if(user)
kexit(ureg);
return;
}
else{
if(vno == VectorNMI){
nmienable();
if(machp()->machno != 0){
iprint("cpu%d: PC %#llx\n",
machp()->machno, ureg->ip);
for(;;);
}
}
dumpregs(ureg);
if(!user){
ureg->sp = PTR2UINT(&ureg->sp);
dumpstackwithureg(ureg);
}
if(vno < nelem(excname))
panic("%s", excname[vno]);
panic("unknown trap/intr: %d\n", vno);
}
splhi();
/* delaysched set because we held a lock or because our quantum ended */
if(up && up->delaysched && clockintr){
if(0)
if(user && up->ac == nil && up->nqtrap == 0 && up->nqsyscall == 0){
if(!waserror()){
up->ac = getac(up, -1);
poperror();
runacore();
return;
}
}
sched();
splhi();
}
if(user){
if(up != nil && (up->procctl || up->nnote))
notify(ureg);
kexit(ureg);
}
}
