static void msm_bus_noc_set_qos_bw(struct msm_bus_noc_info *ninfo,
uint32_t mport, uint8_t perm_mode, struct msm_bus_noc_qos_bw *qbw)
{
uint32_t reg_val, val, mode;
if (!ninfo->qos_freq) {
MSM_BUS_DBG("Zero QoS Freq\n");
return;
}
/* If Limiter or Regulator modes are not supported, bw not available*/
if (perm_mode & (NOC_QOS_PERM_MODE_LIMITER |
NOC_QOS_PERM_MODE_REGULATOR)) {
uint32_t bw_val = noc_bw_field(qbw->bw, ninfo->qos_freq);
uint32_t sat_val = noc_sat_field(qbw->bw, qbw->ws,
ninfo->qos_freq);
MSM_BUS_DBG("NOC: BW: perm_mode: %d bw_val: %d, sat_val: %d\n",
perm_mode, bw_val, sat_val);
/*
* If in Limiter/Regulator mode, first go to fixed mode.
* Clear QoS accumulator
**/
mode = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base,
mport)) & NOC_QOS_MODEn_MODE_BMSK;
if (mode == NOC_QOS_MODE_REGULATOR || mode ==
NOC_QOS_MODE_LIMITER) {
reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->
base, mport));
val = NOC_QOS_MODE_FIXED;
writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
| (val & NOC_QOS_MODEn_MODE_BMSK),
NOC_QOS_MODEn_ADDR(ninfo->base, mport));
}
reg_val = readl_relaxed(NOC_QOS_BWn_ADDR(ninfo->base, mport));
val = bw_val << NOC_QOS_BWn_BW_SHFT;
writel_relaxed(((reg_val & (~(NOC_QOS_BWn_BW_BMSK))) |
(val & NOC_QOS_BWn_BW_BMSK)),
NOC_QOS_BWn_ADDR(ninfo->base, mport));
MSM_BUS_DBG("NOC: BW: Wrote value: 0x%x\n", ((reg_val &
(~NOC_QOS_BWn_BW_BMSK)) | (val &
NOC_QOS_BWn_BW_BMSK)));
reg_val = readl_relaxed(NOC_QOS_SATn_ADDR(ninfo->base,
mport));
val = sat_val << NOC_QOS_SATn_SAT_SHFT;
writel_relaxed(((reg_val & (~(NOC_QOS_SATn_SAT_BMSK))) |
(val & NOC_QOS_SATn_SAT_BMSK)),
NOC_QOS_SATn_ADDR(ninfo->base, mport));
MSM_BUS_DBG("NOC: SAT: Wrote value: 0x%x\n", ((reg_val &
(~NOC_QOS_SATn_SAT_BMSK)) | (val &
NOC_QOS_SATn_SAT_BMSK)));
/* Set mode back to what it was initially */
reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base,
mport));
writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
| (mode & NOC_QOS_MODEn_MODE_BMSK),
NOC_QOS_MODEn_ADDR(ninfo->base, mport));
/* Ensure that all writes for bandwidth registers have
* completed before returning
*/
wmb();
}
}
static void msm_bus_noc_set_qos_bw(struct msm_bus_noc_info *ninfo,
uint32_t mport, uint8_t perm_mode, struct msm_bus_noc_qos_bw *qbw)
{
uint32_t reg_val, val, mode;
if (!ninfo->qos_freq) {
MSM_BUS_DBG("Zero QoS Freq\n");
return;
}
if (perm_mode & (NOC_QOS_PERM_MODE_LIMITER |
NOC_QOS_PERM_MODE_REGULATOR)) {
uint32_t bw_val = noc_bw_field(qbw->bw, ninfo->qos_freq);
uint32_t sat_val = noc_sat_field(qbw->bw, qbw->ws,
ninfo->qos_freq);
MSM_BUS_DBG("NOC: BW: perm_mode: %d bw_val: %d, sat_val: %d\n",
perm_mode, bw_val, sat_val);
mode = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base,
mport)) & NOC_QOS_MODEn_MODE_BMSK;
if (mode == NOC_QOS_MODE_REGULATOR || mode ==
NOC_QOS_MODE_LIMITER) {
reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->
base, mport));
val = NOC_QOS_MODE_FIXED;
writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
| (val & NOC_QOS_MODEn_MODE_BMSK),
NOC_QOS_MODEn_ADDR(ninfo->base, mport));
}
reg_val = readl_relaxed(NOC_QOS_BWn_ADDR(ninfo->base, mport));
val = bw_val << NOC_QOS_BWn_BW_SHFT;
writel_relaxed(((reg_val & (~(NOC_QOS_BWn_BW_BMSK))) |
(val & NOC_QOS_BWn_BW_BMSK)),
NOC_QOS_BWn_ADDR(ninfo->base, mport));
MSM_BUS_DBG("NOC: BW: Wrote value: 0x%x\n", ((reg_val &
(~NOC_QOS_BWn_BW_BMSK)) | (val &
NOC_QOS_BWn_BW_BMSK)));
reg_val = readl_relaxed(NOC_QOS_SATn_ADDR(ninfo->base,
mport));
val = sat_val << NOC_QOS_SATn_SAT_SHFT;
writel_relaxed(((reg_val & (~(NOC_QOS_SATn_SAT_BMSK))) |
(val & NOC_QOS_SATn_SAT_BMSK)),
NOC_QOS_SATn_ADDR(ninfo->base, mport));
MSM_BUS_DBG("NOC: SAT: Wrote value: 0x%x\n", ((reg_val &
(~NOC_QOS_SATn_SAT_BMSK)) | (val &
NOC_QOS_SATn_SAT_BMSK)));
reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(ninfo->base,
mport));
writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
| (mode & NOC_QOS_MODEn_MODE_BMSK),
NOC_QOS_MODEn_ADDR(ninfo->base, mport));
wmb();
}
}