void plat_rockchip_pmu_init(void) { uint32_t cpu; rockchip_pd_lock_init(); plat_setup_rockchip_pm_ops(&pm_ops); /* register requires 32bits mode, switch it to 32 bits */ cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) cpuson_flags[cpu] = 0; psram_sleep_cfg->ddr_func = 0x00; psram_sleep_cfg->ddr_data = 0x00; psram_sleep_cfg->ddr_flag = 0x00; psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; /* cpu boot from pmusram */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); nonboot_cpus_off(); INFO("%s(%d): pd status %x\n", __func__, __LINE__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); }
static int sys_pwr_domain_suspend(void) { nonboot_cpus_off(); pmu_set_sleep_mode(); psram_sleep_cfg->sys_mode = PMU_SYS_SLP_MODE; psram_sleep_cfg->ddr_flag = 0; return 0; }
void plat_rockchip_pmu_init(void) { uint32_t cpu; plat_setup_rockchip_pm_ops(&pm_ops); for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) cpuson_flags[cpu] = 0; psram_sleep_cfg->sys_mode = PMU_SYS_ON_MODE; psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; nonboot_cpus_off(); INFO("%s(%d): pd status %x\n", __func__, __LINE__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); }