static int
nv50_disp_pioc_init(struct nouveau_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
int chid = pioc->base.chid;
int ret;
ret = nv50_disp_chan_init(&pioc->base);
if (ret)
return ret;
nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);
if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {
nv_error(pioc, "timeout0: 0x%08x\n",
nv_rd32(priv, 0x610200 + (chid * 0x10)));
return -EBUSY;
}
nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);
if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {
nv_error(pioc, "timeout1: 0x%08x\n",
nv_rd32(priv, 0x610200 + (chid * 0x10)));
return -EBUSY;
}
return 0;
}
static int
nvd0_disp_pioc_init(struct nouveau_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_pioc *pioc = (void *)object;
int chid = pioc->base.chid;
int ret;
ret = nv50_disp_chan_init(&pioc->base);
if (ret)
return ret;
/* enable error reporting */
nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
/* activate channel */
nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001);
if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) {
nv_error(pioc, "init: 0x%08x\n",
nv_rd32(priv, 0x610490 + (chid * 0x10)));
return -EBUSY;
}
return 0;
}
static int
nv50_disp_dmac_init(struct nouveau_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *dmac = (void *)object;
int chid = dmac->base.chid;
int ret;
ret = nv50_disp_chan_init(&dmac->base);
if (ret)
return ret;
/* enable error reporting */
nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid);
/* initialise channel for dma command submission */
nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);
nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);
nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);
nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);
nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);
/* wait for it to go inactive */
if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {
nv_error(dmac, "init timeout, 0x%08x\n",
nv_rd32(priv, 0x610200 + (chid * 0x10)));
return -EBUSY;
}
return 0;
}
static int
nvd0_disp_mast_init(struct nouveau_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
int ret;
ret = nv50_disp_chan_init(&mast->base);
if (ret)
return ret;
/* enable error reporting */
nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
/* initialise channel for dma command submission */
nv_wr32(priv, 0x610494, mast->push);
nv_wr32(priv, 0x610498, 0x00010000);
nv_wr32(priv, 0x61049c, 0x00000001);
nv_mask(priv, 0x610490, 0x00000010, 0x00000010);
nv_wr32(priv, 0x640000, 0x00000000);
nv_wr32(priv, 0x610490, 0x01000013);
/* wait for it to go inactive */
if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) {
nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490));
return -EBUSY;
}
return 0;
}
static int
nv50_disp_mast_init(struct nouveau_object *object)
{
struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object;
int ret;
ret = nv50_disp_chan_init(&mast->base);
if (ret)
return ret;
/* enable error reporting */
nv_mask(priv, 0x610028, 0x00010001, 0x00010001);
/* attempt to unstick channel from some unknown state */
if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000)
nv_mask(priv, 0x610200, 0x00800000, 0x00800000);
if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000)
nv_mask(priv, 0x610200, 0x00600000, 0x00600000);
/* initialise channel for dma command submission */
nv_wr32(priv, 0x610204, mast->push);
nv_wr32(priv, 0x610208, 0x00010000);
nv_wr32(priv, 0x61020c, 0x00000000);
nv_mask(priv, 0x610200, 0x00000010, 0x00000010);
nv_wr32(priv, 0x640000, 0x00000000);
nv_wr32(priv, 0x610200, 0x01000013);
/* wait for it to go inactive */
if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) {
nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200));
return -EBUSY;
}
return 0;
}