static int
nv84_graph_tlb_flush(struct nouveau_engine *engine)
{
struct nouveau_timer *ptimer = nouveau_timer(engine);
struct nv50_graph_priv *priv = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
u64 start;
u32 tmp;
spin_lock_irqsave(&priv->lock, flags);
nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
start = ptimer->read(ptimer);
do {
idle = true;
for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
if ((tmp & 7) == 1)
idle = false;
}
} while (!idle &&
!(timeout = ptimer->read(ptimer) - start > 2000000000));
if (timeout) {
nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
tmp = nv_rd32(priv, 0x400700);
nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
nouveau_bitfield_print(nv50_pgraph_status, tmp);
pr_cont("\n");
nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
nv_rd32(priv, 0x400380));
nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
nv_rd32(priv, 0x400384));
nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
nv_rd32(priv, 0x400388));
}
nv50_vm_flush_engine(&engine->base, 0x00);
nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
return timeout ? -EBUSY : 0;
}
static int
nv84_crypt_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x0a);
return 0;
}
static int
nv50_graph_tlb_flush(struct nouveau_engine *engine)
{
nv50_vm_flush_engine(&engine->base, 0x00);
return 0;
}
