int __init am33xx_clk_init(void) { if (soc_is_am33xx()) cpu_mask = RATE_IN_AM33XX; omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always * physically present, in such a case HWMOD enabling of * clock would be failure with default parent. And timer * probe thinks clock is already enabled, this leads to * crash upon accessing timer 3 & 6 registers in probe. * Fix by setting parent of both these timers to master * oscillator clock. */ clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); /* * The On-Chip 32K RC Osc clock is not an accurate clock-source as per * the design/spec, so as a result, for example, timer which supposed * to get expired @60Sec, but will expire somewhere ~@40Sec, which is * not expected by any use-case, so change WDT1 clock source to PRCM * 32KHz clock. */ clk_set_parent(&wdt1_fck, &clkdiv32k_ick); return 0; }
int __init dm816x_dt_clk_init(void) { ti_dt_clocks_register(dm816x_clks); omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); return 0; }
static int __init omap3xxx_clk_init(int soc_type) { of_clk_init(NULL); if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_OMAP3430_ES1 || soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) omap_dt_clocks_register(omap3xxx_clks); if (soc_type == OMAP3_SOC_AM35XX) omap_dt_clocks_register(am35xx_clks); if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) omap_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks); if (soc_type == OMAP3_SOC_OMAP3430_ES1) omap_dt_clocks_register(omap3430es1_clks); if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || soc_type == OMAP3_SOC_OMAP3630) omap_dt_clocks_register(omap36xx_omap3430es2plus_clks); if (soc_type == OMAP3_SOC_OMAP3430_ES1 || soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || soc_type == OMAP3_SOC_OMAP3630) omap_dt_clocks_register(omap34xx_omap36xx_clks); omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) omap3_clk_lock_dpll5(); return 0; }
int __init am33xx_clk_init(void) { struct omap_clk *c; u32 cpu_clkflg; if (soc_is_am33xx()) { cpu_mask = RATE_IN_AM33XX; cpu_clkflg = CK_AM33XX; } for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); if (!__clk_init(NULL, c->lk.clk)) omap2_init_clk_hw_omap_clocks(c->lk.clk); } } omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always * physically present, in such a case HWMOD enabling of * clock would be failure with default parent. And timer * probe thinks clock is already enabled, this leads to * crash upon accessing timer 3 & 6 registers in probe. * Fix by setting parent of both these timers to master * oscillator clock. */ clk_set_parent(&timer3_fck, &sys_clkin_ck); clk_set_parent(&timer6_fck, &sys_clkin_ck); return 0; }
static int __init omap2xxx_dt_clk_init(int soc_type) { ti_dt_clocks_register(omap2xxx_clks); if (soc_type == OMAP2_SOC_OMAP2420) ti_dt_clocks_register(omap2420_clks); else ti_dt_clocks_register(omap2430_clks); omap2xxx_clkt_vps_init(); omap2_clk_disable_autoidle_all(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), (clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, (clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), (clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); return 0; }