static void omap8250_update_mdr1(struct uart_8250_port *up, struct omap8250_priv *priv) { if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) omap_8250_mdr1_errataset(up, priv); else serial_out(up, UART_OMAP_MDR1, priv->mdr1); }
static void omap8250_restore_regs(struct uart_8250_port *up) { struct omap8250_priv *priv = up->port.private_data; struct uart_8250_dma *dma = up->dma; if (dma && dma->tx_running) { /* * TCSANOW requests the change to occur immediately however if * we have a TX-DMA operation in progress then it has been * observed that it might stall and never complete. Therefore we * delay DMA completes to prevent this hang from happen. */ priv->delayed_restore = 1; return; } serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, UART_EFR_ECB); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, UART_MCR_TCRTLR); serial_out(up, UART_FCR, up->fcr); omap8250_update_scr(up, priv); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | OMAP_UART_TCR_HALT(52)); serial_out(up, UART_TI752_TLR, TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); serial_out(up, UART_LCR, 0); /* drop TCR + TLR access, we setup XON/XOFF later */ serial_out(up, UART_MCR, up->mcr); serial_out(up, UART_IER, up->ier); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_dl_write(up, priv->quot); serial_out(up, UART_EFR, priv->efr); /* Configure flow control */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_XON1, priv->xon); serial_out(up, UART_XOFF1, priv->xoff); serial_out(up, UART_LCR, up->lcr); /* need mode A for FCR */ if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) omap_8250_mdr1_errataset(up, priv); else serial_out(up, UART_OMAP_MDR1, priv->mdr1); up->port.ops->set_mctrl(&up->port, up->port.mctrl); }