/**
* omap_pmic_register_data() - Register the PMIC information to OMAP mapping
* @omap_pmic_maps: array ending with a empty element representing the maps
* @desc: description for this PMIC.
*/
int __init omap_pmic_register_data(struct omap_pmic_map *omap_pmic_maps,
struct omap_pmic_description *desc)
{
struct voltagedomain *voltdm;
struct omap_pmic_map *map;
int r;
if (!omap_pmic_maps)
return 0;
map = omap_pmic_maps;
while (map->name) {
if (!omap_chip_is(map->omap_chip))
goto next;
/* The base PMIC is the one controlling core voltdm */
if (desc && !strcmp(map->name, "core"))
omap_pm_set_pmic_lp_time(desc->pmic_lp_tstart,
desc->pmic_lp_tshut);
voltdm = voltdm_lookup(map->name);
if (IS_ERR_OR_NULL(voltdm)) {
pr_err("%s: unable to find map %s\n", __func__,
map->name);
goto next;
}
if (IS_ERR_OR_NULL(map->pmic_data)) {
pr_warning("%s: domain[%s] has no pmic data\n",
__func__, map->name);
goto next;
}
r = omap_voltage_register_pmic(voltdm, map->pmic_data);
if (r) {
pr_warning("%s: domain[%s] register returned %d\n",
__func__, map->name, r);
goto next;
}
if (map->special_action) {
r = map->special_action(voltdm);
WARN(r, "%s: domain[%s] action returned %d\n", __func__,
map->name, r);
}
next:
map++;
}
return 0;
}
static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
/* PRM accesses are slow, so minimize them */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->sleepdep_usecount, 0);
}
omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
OMAP3430_CM_SLEEPDEP);
return 0;
}
static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
{
struct clkdm_dep *cd;
u32 mask = 0;
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
if (!omap_chip_is(cd->omap_chip))
continue;
if (!cd->clkdm)
continue; /* only happens if data is erroneous */
mask |= 1 << cd->clkdm->dep_bit;
atomic_set(&cd->wkdep_usecount, 0);
}
omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs +
OMAP4_CM_STATICDEP);
return 0;
}
static int hdmi_audio_set_configuration(struct hdmi_codec_data *priv)
{
struct hdmi_audio_format *audio_format = &priv->audio_fmt;
struct hdmi_audio_dma *audio_dma = &priv->audio_dma;
struct hdmi_core_audio_config *core_cfg = &priv->audio_core_cfg;
struct hdmi_core_infoframe_audio *aud_if_cfg = &priv->aud_if_cfg;
int err, n, cts, channel_alloc;
enum hdmi_core_audio_sample_freq sample_freq;
u32 pclk = omapdss_hdmi_get_pixel_clock();
struct omap_chip_id audio_must_use_mclk;
audio_must_use_mclk.oc = CHIP_IS_OMAP4430ES2_3 | CHIP_IS_OMAP446X |
CHIP_IS_OMAP447X;
switch (priv->params.format) {
case SNDRV_PCM_FORMAT_S16_LE:
core_cfg->i2s_cfg.word_max_length =
HDMI_AUDIO_I2S_MAX_WORD_20BITS;
core_cfg->i2s_cfg.word_length =
HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
core_cfg->i2s_cfg.in_length_bits =
HDMI_AUDIO_I2S_INPUT_LENGTH_16;
core_cfg->i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
audio_format->samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
audio_format->sample_size = HDMI_AUDIO_SAMPLE_16BITS;
audio_format->justification = HDMI_AUDIO_JUSTIFY_LEFT;
audio_dma->transfer_size = 0x10;
break;
case SNDRV_PCM_FORMAT_S24_LE:
core_cfg->i2s_cfg.word_max_length =
HDMI_AUDIO_I2S_MAX_WORD_24BITS;
core_cfg->i2s_cfg.word_length =
HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
core_cfg->i2s_cfg.in_length_bits =
HDMI_AUDIO_I2S_INPUT_LENGTH_24;
audio_format->samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
audio_format->sample_size = HDMI_AUDIO_SAMPLE_24BITS;
audio_format->justification = HDMI_AUDIO_JUSTIFY_RIGHT;
core_cfg->i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
audio_dma->transfer_size = 0x20;
break;
default:
return -EINVAL;
}
switch (priv->params.sample_freq) {
case 32000:
sample_freq = HDMI_AUDIO_FS_32000;
break;
case 44100:
sample_freq = HDMI_AUDIO_FS_44100;
break;
case 48000:
sample_freq = HDMI_AUDIO_FS_48000;
break;
default:
return -EINVAL;
}
err = hdmi_ti_4xxx_config_audio_acr(&priv->ip_data,
priv->params.sample_freq, &n, &cts, pclk);
if (err < 0)
return err;
/* Audio wrapper config */
audio_format->type = HDMI_AUDIO_TYPE_LPCM;
audio_format->sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
/* Disable start/stop signals of IEC 60958 blocks */
audio_format->en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
audio_dma->block_size = 0xC0;
audio_dma->mode = HDMI_AUDIO_TRANSF_DMA;
audio_dma->fifo_threshold = 0x20; /* in number of samples */
hdmi_ti_4xxx_wp_audio_config_dma(&priv->ip_data, audio_dma);
hdmi_ti_4xxx_wp_audio_config_format(&priv->ip_data, audio_format);
/*
* I2S config
*/
core_cfg->i2s_cfg.en_high_bitrate_aud = false;
/* Only used with high bitrate audio */
core_cfg->i2s_cfg.cbit_order = false;
/* Serial data and word select should change on sck rising edge */
core_cfg->i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
core_cfg->i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
/* Set I2S word select polarity */
core_cfg->i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
core_cfg->i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
/* Set serial data to word select shift. See Phillips spec. */
core_cfg->i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
/* Core audio config */
core_cfg->freq_sample = sample_freq;
core_cfg->n = n;
core_cfg->cts = cts;
if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
core_cfg->aud_par_busclk = 0;
core_cfg->cts_mode = HDMI_AUDIO_CTS_MODE_SW;
core_cfg->use_mclk = omap_chip_is(audio_must_use_mclk);
} else {
core_cfg->aud_par_busclk = (((128 * 31) - 1) << 8);
core_cfg->cts_mode = HDMI_AUDIO_CTS_MODE_HW;
core_cfg->use_mclk = true;
core_cfg->mclk_mode = HDMI_AUDIO_MCLK_128FS;
}
core_cfg->en_spdif = false;
/* Use sample frequency from channel status word */
core_cfg->fs_override = true;
/* Enable ACR packets */
core_cfg->en_acr_pkt = true;
/* Disable direct streaming digital audio */
core_cfg->en_dsd_audio = false;
/* Use parallel audio interface */
core_cfg->en_parallel_aud_input = true;
/* Number of channels */
aud_if_cfg->db1_channel_count = priv->params.channels_nr;
switch (priv->params.channels_nr) {
case 2:
core_cfg->layout = HDMI_AUDIO_LAYOUT_2CH;
channel_alloc = 0x0;
audio_format->stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
audio_format->active_chnnls_msk = 0x03;
/* Enable one of the four available serial data channels */
core_cfg->i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
break;
case 6:
core_cfg->layout = HDMI_AUDIO_LAYOUT_8CH;
channel_alloc = 0x13;
audio_format->stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
audio_format->active_chnnls_msk = 0x3f;
/* Enable all of the four available serial data channels */
core_cfg->i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
HDMI_AUDIO_I2S_SD3_EN;
/*
* Overwrite info frame with channel count = 7 (8-1) and
* CA = 0x13 in order to ensure that sample_present bits
* configuration matches the number of channels (2 channels
* are padded with zeroes) that are sent to fullfil
* multichannel certification tests.
*/
aud_if_cfg->db1_channel_count = 8;
break;
case 8:
core_cfg->layout = HDMI_AUDIO_LAYOUT_8CH;
channel_alloc = 0x13;
audio_format->stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
audio_format->active_chnnls_msk = 0xff;
/* Enable all of the four available serial data channels */
core_cfg->i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
HDMI_AUDIO_I2S_SD3_EN;
break;
default:
pr_err("Unsupported number of channels\n");
return -EINVAL;
}
hdmi_ti_4xxx_core_audio_config(&priv->ip_data, core_cfg);
hdmi_ti_4xxx_wp_audio_config_format(&priv->ip_data, audio_format);
/*
* Configure packet
* info frame audio see doc CEA861-D page 74
*/
aud_if_cfg->db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
aud_if_cfg->db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
aud_if_cfg->db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
aud_if_cfg->db4_channel_alloc = channel_alloc;
aud_if_cfg->db5_downmix_inh = false;
aud_if_cfg->db5_lsv = 0;
hdmi_ti_4xxx_core_audio_infoframe_config(&priv->ip_data, aud_if_cfg);
return 0;
}
