static void omap_pwm_led_power_on(struct omap_pwm_led *led) { pr_debug("%s%s: \n", PASS1,__func__); printk("!!!!!!!!!!%s the brightness is %d \n",__func__, led->brightness); if (led->powered){ printk("!!!!!!!!!!LED powered, returning \n"); return; } led->powered = 1; /* Select clock */ omap_dm_timer_enable(led->intensity_timer); omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_prescaler(led->intensity_timer, 0); /* Turn voltage on */ if (led->pdata->set_power != NULL) { printk("!!!!!!!!!!Turn voltage on \n"); led->pdata->set_power(led->pdata, 1); } /* Enable PWM timers */ if (led->blink_timer != NULL) { printk("!!!!!!!!!!Enable PWM timers \n"); omap_dm_timer_enable(led->blink_timer); omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } omap_dm_timer_set_load(led->intensity_timer, 1, 0xffffff00); }
static void omap_pwm_led_power_on(struct omap_pwm_led *led) { if (led->powered) return; led->powered = 1; /* Select clock */ omap_dm_timer_enable(led->intensity_timer); omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_32_KHZ); /* Turn voltage on */ if (led->pdata->set_power != NULL) led->pdata->set_power(led->pdata, 1); /* Enable PWM timers */ if (led->blink_timer != NULL) { omap_dm_timer_enable(led->blink_timer); omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } omap_dm_timer_write_counter(led->intensity_timer, 0xffffffff); omap_dm_timer_set_load(led->intensity_timer, 1, 0xffffff00); }
static ssize_t store_irblaster_freq(struct device *dev, struct device_attribute *attr, const char* buf, size_t len) { frequency = simple_strtol(buf, NULL, 10); /* Disable pwm */ if (frequency == 0) { omap_dm_timer_stop(irb_pwm_timer); omap_dm_timer_disable(irb_pwm_timer); irb_state = 0; return 0; } /* Enable pwm */ if (irb_state == 0) { omap_dm_timer_enable(irb_pwm_timer); omap_dm_timer_set_pwm(irb_pwm_timer, 0, 1, 2); omap_dm_timer_start(irb_pwm_timer); irb_state = 1; } pwm_set_speed(irb_pwm_timer, frequency, duty_cycle); return len; }
static void set_gptimer_pwm_vibrator(int on) { unsigned long flags; if (pwm_timer == NULL) { pr_err(KERN_ERR "vibrator pwm timer is NULL\n"); return; } spin_lock_irqsave(&vibe__timer_lock, flags); if (on) { if(!vibe_timer_state) { gpio_set_value(GPIO_VIB_EN, 1); omap_dm_timer_enable(pwm_timer); omap_dm_timer_set_match(pwm_timer, 1, 0xFFFFFFFE); omap_dm_timer_set_pwm(pwm_timer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); omap_dm_timer_set_load_start(pwm_timer, 1, MOTOR_RESONANCE_COUTER_VALUE); vibe_timer_state = 1; } } else { if(vibe_timer_state) { omap_dm_timer_stop(pwm_timer); omap_dm_timer_disable(pwm_timer); gpio_set_value(GPIO_VIB_EN, 0); vibe_timer_state = 0; } } spin_unlock_irqrestore(&vibe__timer_lock, flags); }
static void omap_pwm_led_power_on(struct omap_pwm_led *led) { if (led->powered) return; led->powered = 1; pr_debug("%s: brightness: %i\n", __func__, led->brightness); /* Select clock */ omap_dm_timer_set_source(led->intensity_timer, OMAP_TIMER_SRC_SYS_CLK); /* Turn voltage on */ if (led->pdata->set_power != NULL) led->pdata->set_power(led->pdata, 1); /* explicitly enable the timer, saves some SAR later */ omap_dm_timer_enable(led->intensity_timer); /* Enable PWM timers */ if (led->blink_timer != NULL) { omap_dm_timer_set_source(led->blink_timer, OMAP_TIMER_SRC_32_KHZ); omap_pwm_led_set_blink(led); } }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); /* * This code could try requesting registers 9, 10, and 11, * stopping at the first succesful request. We'll stick with * 11 for now, as it avoids having to hard code yet more * physical addresses into the code. */ psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } /* Set timer source to system clock */ omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); /* Set autoreload, and start value of 0 */ omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); /* * The DM timer API doesn't have a mechansim for obtaining the * physical address of the counter register. */ psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE; return PVRSRV_OK; }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3_GPTIMER_REGS_SYS_PHYS_BASE; return PVRSRV_OK; }
static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51) { struct clk *clk_fclk; int retval, pwm_timer = lirc_rx51->pwm_timer_num; lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer); if (lirc_rx51->pwm_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n", pwm_timer); return -EBUSY; } lirc_rx51->pulse_timer = omap_dm_timer_request(); if (lirc_rx51->pulse_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n"); retval = -EBUSY; goto err1; } omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_source(lirc_rx51->pulse_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(lirc_rx51->pwm_timer); omap_dm_timer_enable(lirc_rx51->pulse_timer); lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer); retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler, IRQF_DISABLED | IRQF_SHARED, "lirc_pulse_timer", lirc_rx51); if (retval) { dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n"); goto err2; } clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer); lirc_rx51->fclk_khz = clk_fclk->rate / 1000; return 0; err2: omap_dm_timer_free(lirc_rx51->pulse_timer); err1: omap_dm_timer_free(lirc_rx51->pwm_timer); return retval; }
static void sholest_lvibrator_power_on(void) { #ifdef CONFIG_VIB_PWM gpio_set_value(SHOLEST_VIBRATOR_EN_GPIO, 1); #endif if (vib_pwm_timer == NULL) sholest_lvibrator_initialization(); omap_dm_timer_enable(vib_pwm_timer); omap_dm_timer_start(vib_pwm_timer); }
static int panel_set_backlight_level( struct omap_display *disp, int level) { int hw_level; pr_debug("panel_set_backlight_level [%s] %d\n", disp != NULL ? disp->panel->name: "cpt_wvga_48", level); /* skip if panel is not on */ if (panel_state == 0) { saved_bkl_level = level; return 0; } /* clamp the level */ if (level < 0) level = 0; if (level > 255) level = 255; /* nothing to do if levels are equal */ if (bkl_level == level) return 0; /* stop backlight? */ if (level == 0) { if (GPIO_EXISTS(display_gpio.bkl_pwon)) omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 0); omap_dm_timer_stop(bkl_pwm); omap_dm_timer_disable(bkl_pwm); bkl_level = 0; return 0; } /* start backlight? */ if (bkl_level == 0) { omap_dm_timer_enable(bkl_pwm); omap_dm_timer_set_pwm(bkl_pwm, 0, 1, 2); omap_dm_timer_start(bkl_pwm); if (GPIO_EXISTS(display_gpio.bkl_pwon)) omap_set_gpio_dataout(GPIO_PIN(display_gpio.bkl_pwon), 1); } /* set new level, g7 machines have inverted level */ hw_level = level; if (!machine_is_archos_g6h()) hw_level = 255 - level; pwm_set_speed(bkl_pwm, 10000, hw_level); bkl_level = level; return 0; }
/* * For setting the values in registers for varying the duty cycle and time period */ static void vibtonz_GPTimerSetValue(unsigned long load,unsigned long cmp) { unsigned long load_reg, cmp_reg; // printk("[VIBRATOR] %s \n",__func__); load_reg = load; /* For setting the frequency=22.2Khz */ cmp_reg = cmp; /* For varying the duty cycle */ omap_dm_timer_enable(gptimer); omap_dm_timer_set_load(gptimer, 1, -load_reg); omap_dm_timer_set_match(gptimer, 1, -cmp_reg); omap_dm_timer_set_pwm(gptimer, 0, 1,OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); omap_dm_timer_write_counter(gptimer, -2); omap_dm_timer_save_context(gptimer); }
static void backlight_gptimer_update(struct omap_dss_device *dssdev) { struct ltn101al03 *lcd = dev_get_drvdata(&dssdev->dev); omap_dm_timer_set_load(lcd->gptimer, 1, -PWM_DUTY_MAX); omap_dm_timer_set_match(lcd->gptimer, 1, /* 0~25 */ -PWM_DUTY_MAX + lcd->current_brightness); omap_dm_timer_set_pwm(lcd->gptimer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); omap_dm_timer_enable(lcd->gptimer); omap_dm_timer_write_counter(lcd->gptimer, -2); omap_dm_timer_disable(lcd->gptimer); omap_dm_timer_start(lcd->gptimer); }
/* * Driver Initialization */ static int __init hello_init(void) { int ret; /* Request dynamic allocation of a device major number */ if (alloc_chrdev_region(&my_dev_number, 0, 1, DEVICE_NAME) < 0) { printk(KERN_DEBUG "Can't register device\n"); return -1; } /* Populate sysfs entries */ my_dev_class = class_create(THIS_MODULE, DEVICE_NAME); /* Allocate memory for the per-device structure */ hrt_devp = kmalloc(sizeof(struct HRT_dev), GFP_KERNEL); /* Allocate memory for the timer */ timer = kmalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); /* Request a timer */ timer = omap_dm_timer_request(); /* Set timer source */ omap_dm_timer_set_source(timer,OMAP_TIMER_SRC_SYS_CLK); /* enable the timer */ omap_dm_timer_enable(timer); /* Request I/O region */ sprintf(hrt_devp->name, DEVICE_NAME); /* Connect the file operations with the cdev */ cdev_init(&hrt_devp->cdev, &My_fops); hrt_devp->cdev.owner = THIS_MODULE; /* Connect the major/minor number to the cdev */ ret = cdev_add(&hrt_devp->cdev, (my_dev_number), 1); if (ret) { printk("Bad cdev\n"); return ret; } /* Send uevents to udev, so it'll create /dev nodes */ device_create(my_dev_class, NULL, MKDEV(MAJOR(my_dev_number), 0), NULL, DEVICE_NAME); printk("HRT Driver Initialized.\n"); return 0; }
void pwm_gpt_start(int id) { if ( !_check_id(id) ) { return; } if ( !_check_timer(id) ) { return; } /* enable the timer, start the clock */ omap_dm_timer_enable(gpt_pwm_list[id].timer); /* do not wait for ack, just set up the reg and leave */ /* this is better if you setup 2 correlated timers */ omap_dm_timer_start(gpt_pwm_list[id].timer); }
/*! ****************************************************************************** @Function AcquireGPTimer @Description Acquire a GP timer @Return PVRSRV_ERROR ******************************************************************************/ static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { PVR_ASSERT(psSysSpecData->psGPTimer == NULL); /* * This code has problems on module reload for OMAP5 running Linux * 3.4.10, due to omap2_dm_timer_set_src (called by * omap_dm_timer_request_specific), being unable to set the parent * clock to OMAP_TIMER_SRC_32_KHZ. * Not calling omap_dm_timer_set_source doesn't help. */ #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) || !defined(MODULE) /* * This code could try requesting registers 9, 10, and 11, * stopping at the first succesful request. We'll stick with * 11 for now, as it avoids having to hard code yet more * physical addresses into the code. */ psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); if (psSysSpecData->psGPTimer == NULL) { PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; } omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(psSysSpecData->psGPTimer); /* Set autoreload, and start value of 0 */ omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); omap_dm_timer_start(psSysSpecData->psGPTimer); /* * The DM timer API doesn't have a mechanism for obtaining the * physical address of the counter register. */ psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_REGS_SYS_PHYS_BASE; #else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */ (void)psSysSpecData; #endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0)) || !defined(MODULE) */ return PVRSRV_OK; }
/* * Request dmtimer * TESTED */ struct omap_dm_timer *HRTDriver_reserve_timer(void) { //Get device private data //struct HRT_dev *hrt_devp = file->private_data; struct omap_dm_timer *timer; timer = omap_dm_timer_request(); omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(timer); if (!timer) printk("\nTimer not reserved!\n"); else printk("\nTimer succesfully reserved!\n"); //setting the load enables the timer //omap_dm_timer_set_load_start(hrt_devp->gptimer, 0, 0); omap_dm_timer_start(timer); return timer; }
static int panel_set_vcom_level( struct omap_display *disp, int level) { pr_debug("panel_set_vcom_level [%s] %i\n", disp->panel->name, level); /* clamp the level */ if (level < 0) level = 0; if (level > 255) level = 255; /* nothing to do if levels are equal */ if (vcom_level == level) return 0; /* stop vcom? */ if (level == 0) { omap_dm_timer_stop(vcom_pwm); omap_dm_timer_disable(vcom_pwm); vcom_level = 0; return 0; } /* start vcom? */ if (vcom_level == 0) { omap_dm_timer_enable(vcom_pwm); omap_dm_timer_set_pwm(vcom_pwm, 0, 1, 2); omap_dm_timer_start(vcom_pwm); } vcom_level = level; pwm_set_speed(vcom_pwm, 10000, vcom_level); vcom_level = level; return 0; }
int request_gptimer12( struct gptimer12_timer *timer ) { int loop_count; int empty_slot = -1; unsigned int next_time = 0; unsigned int current_time = 0; //unsigned int temp; unsigned char update_flag = 0; // printk("request_gptimer12 called \n"); if ( gptimer12_count >= MAX_GPTIMER12_INSTANCE ) { printk( "Error... max gptimer12 instance" ); return -1; } //CM_ICLKEN_WKUP |= 1 << 1; cm_val = cm_read_mod_reg( WKUP_MOD, CM_ICLKEN1 ); cm_val = cm_val | ( 1 << 1 ); cm_write_mod_reg( cm_val, WKUP_MOD, CM_ICLKEN1 ); //modify exist entry for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ ) { if ( timer_manager[loop_count].timer.name != NULL ) { if( strcmp( timer_manager[loop_count].timer.name, timer->name ) == 0 ) { //printk("timer update \n"); memcpy( &( timer_manager[loop_count].timer ), timer, sizeof( struct gptimer12_timer ) ); timer_manager[loop_count].remain_time = timer->expire_time; update_flag = 1; } } } next_time = timer->expire_time; if ( update_flag == 0 ) { //add new entry for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ ) { if ( ( timer_manager[loop_count].timer.name ) == NULL ) { empty_slot = loop_count; break; } } //printk("empty_slot : %d, loop_count : %d\n",empty_slot,loop_count); if ( empty_slot == -1 ) { printk("Error.. No empty slot "); return -1; } gptimer12_count++; memcpy(&(timer_manager[empty_slot].timer),timer, sizeof(struct gptimer12_timer)); timer_manager[empty_slot].remain_time = timer->expire_time; // printk("test3 : gptimer12_count : %d\n",gptimer12_count); if ( gptimer12_count == 1 ) { omap_dm_timer_enable( battery_timer ); prcm_wakeup_event_control( PRCM_GPT12, PRCM_ENABLE ); omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW ); omap_dm_timer_set_int_enable( battery_timer, OMAP_TIMER_INT_OVERFLOW ); for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ ) { if ( timer_manager[loop_count].timer.name != NULL ) timer_manager[loop_count].remain_time -= next_time; } omap_dm_timer_set_load_start( battery_timer, 0, 0xffffffff - GP_TIMER12_SEC_TO_TICK(next_time) ); //CM_ICLKEN_WKUP &= ~(1 << 1); #if 0 cm_val = cm_read_mod_reg(WKUP_MOD,CM_ICLKEN1); cm_val = cm_val&~(1<<1); cm_write_mod_reg(cm_val,WKUP_MOD,CM_ICLKEN1); #endif timer->active = true; return 1; } } omap_dm_timer_stop( battery_timer ); //:commented this #if 1 current_time = GP_TIMER12_TICK_TO_SEC( 0xffffffff - omap_dm_timer_read_counter(battery_timer) ); #endif for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ ) { timer_manager[loop_count].remain_time += current_time; #if 0 if((timer_manager[loop_count].timer.name) != 0) { if((timer_manager[loop_count].remain_time) == 0) timer_manager[loop_count].remain_time = current_time; } #endif } for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ ) { if ( timer_manager[loop_count].timer.name != NULL ) { next_time = timer_manager[loop_count].remain_time; break; } } for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ ) { if ( timer_manager[loop_count].timer.name != NULL ) { if ( next_time > timer_manager[loop_count].remain_time ) next_time = timer_manager[loop_count].remain_time; } } for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ ) { if ( timer_manager[loop_count].timer.name != NULL ) timer_manager[loop_count].remain_time -= next_time; } // timer prcm_wakeup_event_control( PRCM_GPT12, PRCM_ENABLE ); omap_dm_timer_set_int_enable( battery_timer, OMAP_TIMER_INT_OVERFLOW ); omap_dm_timer_set_load_start( battery_timer, 0, 0xffffffff - GP_TIMER12_SEC_TO_TICK(next_time) ); //CM_ICLKEN_WKUP &= ~(1 << 1); #if 0 cm_val = cm_read_mod_reg(WKUP_MOD,CM_ICLKEN1); cm_val = cm_val&~(1<<1); cm_write_mod_reg(cm_val,WKUP_MOD,CM_ICLKEN1); // printk("requested gptimer12_count : %d \n",gptimer12_count); #endif timer->active = true; return 1; }
void vibtonzGPtimer_enable() { omap_dm_timer_enable(gptimer); }
/* * ======== WMD_DEH_Notify ======== * DEH error notification function. Informs user about the error. */ void WMD_DEH_Notify(struct DEH_MGR *hDehMgr, u32 ulEventMask, u32 dwErrInfo) { struct DEH_MGR *pDehMgr = (struct DEH_MGR *)hDehMgr; struct WMD_DEV_CONTEXT *pDevContext; u32 memPhysical = 0; u32 HW_MMU_MAX_TLB_COUNT = 31; extern u32 faultAddr; u32 cnt = 0; if (MEM_IsValidHandle(pDehMgr, SIGNATURE)) { printk(KERN_INFO "WMD_DEH_Notify: ********** DEVICE EXCEPTION " "**********\n"); pDevContext = (struct WMD_DEV_CONTEXT *)pDehMgr->hWmdContext; switch (ulEventMask) { case DSP_SYSERROR: /* reset errInfo structure before use */ pDehMgr->errInfo.dwErrMask = DSP_SYSERROR; pDehMgr->errInfo.dwVal1 = 0L; pDehMgr->errInfo.dwVal2 = 0L; pDehMgr->errInfo.dwVal3 = 0L; pDehMgr->errInfo.dwVal1 = dwErrInfo; printk(KERN_ERR "WMD_DEH_Notify: DSP_SYSERROR, errInfo " "= 0x%x\n", dwErrInfo); dump_dl_modules(pDevContext); dump_dsp_stack(pDevContext); break; case DSP_MMUFAULT: /* MMU fault routine should have set err info * structure */ pDehMgr->errInfo.dwErrMask = DSP_MMUFAULT; printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT," "errInfo = 0x%x\n", dwErrInfo); printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, High " "Address = 0x%x\n", (unsigned int)pDehMgr->errInfo.dwVal1); printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, Low " "Address = 0x%x\n", (unsigned int)pDehMgr->errInfo.dwVal2); printk(KERN_INFO "WMD_DEH_Notify: DSP_MMUFAULT, fault " "address = 0x%x\n", (unsigned int)faultAddr); PrintDspTraceBuffer(pDevContext); dump_dl_modules(pDevContext); dummyVaAddr = (u32)MEM_Calloc(sizeof(char) * 0x1000, MEM_PAGED); memPhysical = VirtToPhys(PG_ALIGN_LOW((u32)dummyVaAddr, PG_SIZE_4K)); pDevContext = (struct WMD_DEV_CONTEXT *) pDehMgr->hWmdContext; /* Reset the dynamic mmu index to fixed count if it * exceeds 31. So that the dynmmuindex is always * between the range of standard/fixed entries * and 31. */ if (pDevContext->numTLBEntries > HW_MMU_MAX_TLB_COUNT) { pDevContext->numTLBEntries = pDevContext-> fixedTLBEntries; } HW_MMU_TLBAdd(pDevContext->dwDSPMmuBase, memPhysical, faultAddr, HW_PAGE_SIZE_4KB, 1, &mapAttrs, HW_SET, HW_SET); /* * Send a GP Timer interrupt to DSP * The DSP expects a GP timer interrupt after an * MMU-Fault Request GPTimer */ if (timer) { omap_dm_timer_enable(timer); /* Enable overflow interrupt */ omap_dm_timer_set_int_enable(timer, GPTIMER_IRQ_OVERFLOW); /* * Set counter value to overflow counter after * one tick and start timer */ omap_dm_timer_set_load_start(timer, 0, 0xfffffffe); /* Wait 80us for timer to overflow */ udelay(80); /* Check interrupt status and */ /* wait for interrupt */ cnt = 0; while (!(omap_dm_timer_read_status(timer) & GPTIMER_IRQ_OVERFLOW)) { if (cnt++ >= GPTIMER_IRQ_WAIT_MAX_CNT) { pr_err("%s: GPTimer interrupt" " failed\n", __func__); break; } } } /* Clear MMU interrupt */ HW_MMU_EventAck(pDevContext->dwDSPMmuBase, HW_MMU_TRANSLATION_FAULT); dump_dsp_stack(hDehMgr->hWmdContext); if (timer) omap_dm_timer_disable(timer); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: /* reset errInfo structure before use */ pDehMgr->errInfo.dwErrMask = DSP_PWRERROR; pDehMgr->errInfo.dwVal1 = 0L; pDehMgr->errInfo.dwVal2 = 0L; pDehMgr->errInfo.dwVal3 = 0L; pDehMgr->errInfo.dwVal1 = dwErrInfo; printk(KERN_ERR "WMD_DEH_Notify: DSP_PWRERROR, errInfo " "= 0x%x\n", dwErrInfo); break; #endif /* CONFIG_BRIDGE_NTFY_PWRERR */ #ifdef CONFIG_BRIDGE_WDT3 case DSP_WDTOVERFLOW: pDehMgr->errInfo.dwErrMask = DSP_WDTOVERFLOW; pDehMgr->errInfo.dwVal1 = 0L; pDehMgr->errInfo.dwVal2 = 0L; pDehMgr->errInfo.dwVal3 = 0L; pr_err("WMD_DEH_Notify: DSP_WDTOVERFLOW \n "); break; #endif default: DBG_Trace(DBG_LEVEL6, "WMD_DEH_Notify: Unknown Error, errInfo = " "0x%x\n", dwErrInfo); break; } /* Filter subsequent notifications when an error occurs */ if (pDevContext->dwBrdState != BRD_ERROR) { NTFY_Notify(pDehMgr->hNtfy, ulEventMask); #ifdef CONFIG_BRIDGE_RECOVERY bridge_recover_schedule(); #endif } /* Set the Board state as ERROR */ pDevContext->dwBrdState = BRD_ERROR; /* Disable all the clocks that were enabled by DSP */ (void)DSP_PeripheralClocks_Disable(pDevContext, NULL); #ifdef CONFIG_BRIDGE_WDT3 /* * Avoid the subsequent WDT if it happens once, * also If MMU fault occurs */ dsp_wdt_enable(false); #endif } }
static void gp_irblaster_init(int carrier_frequency, int no_carrier, unsigned short *pt_cycles_list) { u32 val; u32 period; int min_cycle=0x70000000; /* this min cycle can be set to another minimum: but which value ? */ unsigned short *pt = pt_cycles_list; irb_over = 0; //_select_irb_config(); /* find min cycle */ while ( *pt != 0) { if ( *pt < min_cycle ) min_cycle = *pt; pt++; } /* enable timer clock */ omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); irq_irblaster_cycles = pt_cycles_list; if ( no_carrier ) { /* set the callback irq function */ _callback_irblaster_timer_interrupt = omap2_irblaster_timer_interrupt_no_carrier; /* set IRBLASTER TIMER PWM */ /* default output is 0 */ /* toogle */ /* trigger on overflow */ omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,1); /* set frequency */ period = _get_innotech_period(gpt_pwm_list[IRBLASTER_PWM].rate,carrier_frequency); gpt_pwm_list[IRBLASTER_PWM].period = period; /* at init, nothing to do during few cycles */ /* and let say, during min cycle */ val = 0xFFFFFFFF+1-(period*min_cycle); omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_PWM].timer, 1, val); /* set IRBLASTER TIMER CTRL */ /* timer freq is the same as the carrier */ period = _get_innotech_period(gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate,carrier_frequency); gpt_pwm_list[IRBLASTER_TIMER_CTRL].period = period; /* at init, nothing to do during few cycles */ /* and let say, during min cycle */ val = 0xFFFFFFFF+1-(period*min_cycle); omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val); /* prepare the irblaster match condition */ /* irblaster timer run twice time faster than the pwm */ /* so this match is set on the middle of the min cycle time */ val = 0xFFFFFFFF+1-(period*min_cycle/2); omap_dm_timer_set_match(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val); } else { /* set the callback irq function */ _callback_irblaster_timer_interrupt = omap2_irblaster_timer_interrupt_carrier; /* set IRBLASTER TIMER PWM */ /* default output is 0 */ /* toogle */ /* trigger on match and overflow */ omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2); /* set waveform frequency and duty cycle 1/2 = 128/256 */ _set_innotech_speed(IRBLASTER_PWM,carrier_frequency,128); /* at init, no trigger = default output on pin */ irq_irblaster_pwm_ctrl_reg = omap_dm_timer_read_reg(gpt_pwm_list[IRBLASTER_PWM].timer, OMAP_TIMER_CTRL_REG); irq_irblaster_pwm_ctrl_reg &= ~(3<<10); omap_dm_timer_write_reg(gpt_pwm_list[IRBLASTER_PWM].timer, OMAP_TIMER_CTRL_REG, irq_irblaster_pwm_ctrl_reg); /* make the start readuy */ irq_irblaster_pwm_ctrl_reg |= OMAP_TIMER_CTRL_ST; /* set IRBLASTER TIMER CTRL */ /* timer freq is the same as the carrier */ period = _get_innotech_period(gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate,carrier_frequency); gpt_pwm_list[IRBLASTER_TIMER_CTRL].period = period; /* at init, nothing to do during few cycles */ /* and let say, during min cycle */ val = 0xFFFFFFFF+1-(period*(*irq_irblaster_cycles)); omap_dm_timer_set_load(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1, val); /* set the irblaster ctrl timer match condition */ /* to the middle of min cycle */ /* from (end_of_cycle - min_cycle/2) to end_of_cycle, */ /* the timer ctrl irq will pool ...*/ // val = 0xFFFFFFFF+1-(period*min_cycle/2); val = 0xFFFFFFFF+1-_get_best_match_timing_int(min_cycle,gpt_pwm_list[IRBLASTER_TIMER_CTRL].period,gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate); omap_dm_timer_set_match(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 1,val ); } omap_dm_timer_start(gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer); omap_dm_timer_start(gpt_pwm_list[ IRBLASTER_PWM].timer); }
/* * ======== bridge_deh_notify ======== * DEH error notification function. Informs user about the error. */ void bridge_deh_notify(struct deh_mgr *hdeh_mgr, u32 ulEventMask, u32 dwErrInfo) { struct deh_mgr *deh_mgr_obj = (struct deh_mgr *)hdeh_mgr; struct wmd_dev_context *dev_context; int status = 0; u32 mem_physical = 0; u32 hw_mmu_max_tlb_count = 31; extern u32 fault_addr; struct cfg_hostres *resources; hw_status hw_status_obj; u32 cnt = 0; if (deh_mgr_obj) { printk(KERN_INFO "bridge_deh_notify: ********** DEVICE EXCEPTION " "**********\n"); dev_context = (struct wmd_dev_context *)deh_mgr_obj->hwmd_context; resources = dev_context->resources; switch (ulEventMask) { case DSP_SYSERROR: /* reset err_info structure before use */ deh_mgr_obj->err_info.dw_err_mask = DSP_SYSERROR; deh_mgr_obj->err_info.dw_val1 = 0L; deh_mgr_obj->err_info.dw_val2 = 0L; deh_mgr_obj->err_info.dw_val3 = 0L; deh_mgr_obj->err_info.dw_val1 = dwErrInfo; printk(KERN_ERR "bridge_deh_notify: DSP_SYSERROR, err_info " "= 0x%x\n", dwErrInfo); dump_dl_modules(dev_context); dump_dsp_stack(dev_context); break; case DSP_MMUFAULT: /* MMU fault routine should have set err info * structure */ deh_mgr_obj->err_info.dw_err_mask = DSP_MMUFAULT; printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT," "err_info = 0x%x\n", dwErrInfo); printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT, High " "Address = 0x%x\n", (unsigned int)deh_mgr_obj->err_info.dw_val1); printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT, Low " "Address = 0x%x\n", (unsigned int)deh_mgr_obj->err_info.dw_val2); printk(KERN_INFO "bridge_deh_notify: DSP_MMUFAULT, fault " "address = 0x%x\n", (unsigned int)fault_addr); dummy_va_addr = (u32) kzalloc(sizeof(char) * 0x1000, GFP_ATOMIC); mem_physical = VIRT_TO_PHYS(PG_ALIGN_LOW ((u32) dummy_va_addr, PG_SIZE4K)); dev_context = (struct wmd_dev_context *) deh_mgr_obj->hwmd_context; print_dsp_trace_buffer(dev_context); dump_dl_modules(dev_context); /* Reset the dynamic mmu index to fixed count if it * exceeds 31. So that the dynmmuindex is always * between the range of standard/fixed entries * and 31. */ if (dev_context->num_tlb_entries > hw_mmu_max_tlb_count) { dev_context->num_tlb_entries = dev_context->fixed_tlb_entries; } if (DSP_SUCCEEDED(status)) { hw_status_obj = hw_mmu_tlb_add(resources->dw_dmmu_base, mem_physical, fault_addr, HW_PAGE_SIZE4KB, 1, &map_attrs, HW_SET, HW_SET); } /* * Send a GP Timer interrupt to DSP * The DSP expects a GP timer interrupt after an * MMU-Fault Request GPTimer */ if (timer) { omap_dm_timer_enable(timer); /* Enable overflow interrupt */ omap_dm_timer_set_int_enable(timer, GPTIMER_IRQ_OVERFLOW); /* * Set counter value to overflow counter after * one tick and start timer */ omap_dm_timer_set_load_start(timer, 0, 0xfffffffe); /* Wait 80us for timer to overflow */ udelay(80); /* * Check interrupt status and * wait for interrupt */ cnt = 0; while (!(omap_dm_timer_read_status(timer) & GPTIMER_IRQ_OVERFLOW)) { if (cnt++ >= GPTIMER_IRQ_WAIT_MAX_CNT) { pr_err("%s: GPTimer interrupt" " failed\n", __func__); break; } } } /* Clear MMU interrupt */ hw_mmu_event_ack(resources->dw_dmmu_base, HW_MMU_TRANSLATION_FAULT); dump_dsp_stack(deh_mgr_obj->hwmd_context); if (timer) omap_dm_timer_disable(timer); break; #ifdef CONFIG_BRIDGE_NTFY_PWRERR case DSP_PWRERROR: /* reset err_info structure before use */ deh_mgr_obj->err_info.dw_err_mask = DSP_PWRERROR; deh_mgr_obj->err_info.dw_val1 = 0L; deh_mgr_obj->err_info.dw_val2 = 0L; deh_mgr_obj->err_info.dw_val3 = 0L; deh_mgr_obj->err_info.dw_val1 = dwErrInfo; printk(KERN_ERR "bridge_deh_notify: DSP_PWRERROR, err_info " "= 0x%x\n", dwErrInfo); break; #endif /* CONFIG_BRIDGE_NTFY_PWRERR */ #ifdef CONFIG_BRIDGE_WDT3 case DSP_WDTOVERFLOW: deh_mgr_obj->err_info.dw_err_mask = DSP_WDTOVERFLOW; deh_mgr_obj->err_info.dw_val1 = 0L; deh_mgr_obj->err_info.dw_val2 = 0L; deh_mgr_obj->err_info.dw_val3 = 0L; pr_err("bridge_deh_notify: DSP_WDTOVERFLOW\n "); break; #endif default: dev_dbg(bridge, "%s: Unknown Error, err_info = 0x%x\n", __func__, dwErrInfo); break; } /* Filter subsequent notifications when an error occurs */ if (dev_context->dw_brd_state != BRD_ERROR) { ntfy_notify(deh_mgr_obj->ntfy_obj, ulEventMask); #ifdef CONFIG_BRIDGE_RECOVERY bridge_recover_schedule(); #endif } /* Set the Board state as ERROR */ dev_context->dw_brd_state = BRD_ERROR; /* Disable all the clocks that were enabled by DSP */ (void)dsp_peripheral_clocks_disable(dev_context, NULL); #ifdef CONFIG_BRIDGE_WDT3 /* * Avoid the subsequent WDT if it happens once, * also If MMU fault occurs */ dsp_wdt_enable(false); #endif } }
static int _init_gpt(void) { int irqno; int ret = 0; if ((gpt_pwm_list[IRBLASTER_PWM].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_PWM].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_PWM].timer, gpt_pwm_list[IRBLASTER_PWM].source); gpt_pwm_list[IRBLASTER_PWM].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_PWM].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no, gpt_pwm_list[IRBLASTER_PWM].rate); if ((gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_TIMER_CTRL].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, gpt_pwm_list[IRBLASTER_TIMER_CTRL].source); gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no, gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate); /* select irblaster configuration */ _select_irb_config(); /* enable timer clock */ omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); /* set modulation mod */ /* trigger on overflow and match */ omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2); omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 0, 1, 2); //if ( gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config ) // omap_cfg_reg(gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config); irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); if (request_irq(irqno, omap2_irblaster_timer_interrupt, IRQF_DISABLED, "gp timer", NULL)) { ret = -EBUSY; goto failed_request_irq; } omap_dm_timer_set_int_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, IRBLASTER_TIMER_CTRL_IT_TYPE); /* disable timer clocks after init */ omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_PWM].timer); init_waitqueue_head(&irb_wait); _gio_debug_init(); return 0; failed_request_irq: omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); return ret; }