static int camif_open(void)
{
int ret;
if (!this->camera)
return 0;
// Camera interrupt
if ((ret = request_irq(INT_CAMERA, camera_interrupt, SA_INTERRUPT,
"camera", NULL))) {
err("Failed to acquire camera interrupt\n");
return ret;
}
#ifndef NO_CAM_DMA
if ((ret = omap_request_dma(eCameraRx, "camera dma", dma_callback,
NULL, (dma_regs_t **)&camera_dma_regs))) {
err("No DMA available for camera\n");
camera_dma_regs = NULL;
return ret;
}
//dbg("Camera DMA at %p\n", camera_dma_regs);
omap_dma_setup(eCameraRx, eDmaIn);
#endif
CameraFPGAEnable();
camif_start(current_exclk);
if ((ret = this->camera->open())) {
err("Error from Camera open\n");
return ret;
}
#ifdef MEASURE_FR
dmac_sum = dmac_delta = dmac_N = 0;
#endif
/*
* wait a few frames for camera to stabilize
*/
camif_wait_for_vsync_edge(EN_V_DOWN);
camif_wait_for_vsync_edge(EN_V_DOWN);
camif_wait_for_vsync_edge(EN_V_DOWN);
return ret;
}
static void omap1610_audio_init(void *dummy)
{
u16 tmp;
FN_IN;
/* check that open mode is correct */
if(openMode & FMODE_WRITE || openMode & FMODE_READ){
}else{
printk("Incorrect open mode: %s:%d %s\n",__FILE__,__LINE__,__FUNCTION__);
FN_OUT(1);
return;
}
/*
Now here's an ugly hack. To use McBSP1, you need to enable
a clock on the DSP. So enable the MPUI, set the clock,
and start the DSP.
An even uglier, evil hack. If this is going to take the DSP
out of reset, shove an idle loop at the reset vector
and make it loop instead of crash. You will still see
a DSP watchdog timer go off.
I would prefer having a DSP program (probably the MP3 decoder) set
up the DSP, but this allows an ARM-only MP3 decoder to work. With
this code, the DSP is never put into idle, so the OMAP chip cannot
go into any decent low-power mode. Also, all of the DSP interface
dependencies (such as MPUI_STROBE settings) would be taken care
of. Plus, we wouldn't have to worry about different boot vector
addresses depending on the chip version.
*/
{
u32 boot_vector;
u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
tmp = inw(0xfffece10); /* read ARM_RSTCT1 register */
if (0 == (tmp & 0x6)) { /* check if DSP is up */
DPRINTK(__FUNCTION__ ": Bringing DSP out of reset.\n");
if (0 == (tmp & 0x4)) { /* MPUI in reset */
tmp |= 0x4;
outw(tmp, 0xfffece10);
ck_enable(api_ck);
}
tmp = inw(0xe1008008); /* read DSP_IDLECT2 register */
if (6 != (tmp & 0x6)) { /* DSP CLKM enable */
tmp |= 0x6;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014); /* read DSP_RSTCT2 register */
if (3 != (tmp & 0x3)) { /* DSP PER_EN bit */
tmp |= 0x3;
outw(tmp, 0xe1008014);
}
tmp = inw(0xfffece00); /* read ARM_CKCTL register */
tmp |= 0x2000;
outw(tmp, 0xfffece00);
/* Write C55 code at reset vector. */
DPRINTK(__FUNCTION__ ": Bringing DSP out of reset - in progress.\n");
boot_vector = 0x10000;
memcpy((void *)(OMAP_DSP_BASE + boot_vector),
&c55_start,
sizeof(c55_start));
outw(0x5, 0xfffec918); /* Set DSP boot mode */
tmp = inw(0xfffece10); /* take DSP out of reset */
tmp |= 0x6;
outw(tmp, 0xfffece10);
}
else { /* DSP's up, just check the clock/per bits */
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { /* DSP CLKM enable */
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { /* DSP PER_EN bit */
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
}
}
/*
Configure the DMA channel and MCBSP.
*/
DPRINTK(__FUNCTION__ ": Configure DMA output channel. output_stream.dma_regs: %p\n", output_stream.dma_regs);
DPRINTK(__FUNCTION__ ": Configure DMA input channel. input_stream.dma_regs: %p\n", input_stream.dma_regs);
if(openMode & FMODE_WRITE){
/* Setup DMA channel to McBSP1 audio Tx. */
output_stream.dma_regs->csdp = 0x0a01;
output_stream.dma_regs->ccr |= 0x1400;/* !!!!! source auto increment, don't enable yet */
output_stream.dma_regs->cicr = 0x23;
output_stream.dma_regs->cdsa_l = ((OMAP1610_MCBSP1_BASE + 0x806) & 0xffff); /* McBSP1 DXR1 */
output_stream.dma_regs->cdsa_u = ((OMAP1610_MCBSP1_BASE + 0x806) >> 16);
output_stream.dma_regs->cfn = 0x1;
omap_dma_setup(audio_state.output_stream->dma_dev, eDmaOut);
}/* if(openMode & FMODE_WRITE) */
static void omap1510_audio_init(void *dummy)
{
dma_regs_t *dma_regs = output_stream.dma_regs;
u8 fpga;
printk(__FUNCTION__ "called\n");
/*
Init FPGA.
Turn on Audio amplifier and set 12.288 MHz clock
*/
fpga = fpga_read(OMAP1510P1_FPGA_POWER);
fpga &= 0xfe;
fpga_write(fpga, OMAP1510P1_FPGA_POWER);
fpga = 0xc;
fpga_write(fpga, OMAP1510P1_FPGA_AUDIO);
#ifndef CONFIG_DSP_MCBSP1
/*
Now here's an ugly hack. To use McBSP1, you need to enable
a clock on the DSP. So enable the MPUI, set the clock,
and start the DSP.
An even uglier, evil hack. If this is going to take the DSP
out of reset, shove an idle loop at the reset vector
and make it loop instead of crash. You will still see
a DSP watchdog timer go off.
*/
{
u16 tmp;
u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
tmp = inw(ARM_RSTCT1);
// check if DSP is up
if (!(tmp & (ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN))) {
if (!(tmp & ARM_RSTCT1_DSP_RST)) { // MPUI in reset
tmp |= ARM_RSTCT1_DSP_RST;
outw(tmp, ARM_RSTCT1);
ck_enable(api_ck);
}
// REVISIT: I'm not finding this in the OMAP1509 TRM:
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { // DSP CLKM enable
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { // DSP PER_EN bit
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
tmp = inw(ARM_CKCTL); // Enable DSP
tmp |= 0x2000;
outw(tmp, ARM_CKCTL);
// Write C55 code at reset vector.
memcpy((OMAP_DSP_BASE + 0x4c000),
&c55_start,
sizeof(c55_start));
outw(0x5, MPUI_DSP_BOOT_CONFIG); // Set DSP boot mode
tmp = inw(ARM_RSTCT1); // take DSP out of reset
tmp |= ARM_RSTCT1_DSP_RST|ARM_RSTCT1_DSP_EN;
outw(tmp, ARM_RSTCT1);
} else {
// DSP's up, just check the clock/per bits
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { // DSP CLKM enable
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { // DSP PER_EN bit
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
}
}
/*
While we're waiting for the UDA1341 to wake up, let's configure the
DMA channel and MCBSP.
*/
// Setup DMA channel to McBSP1 audio Tx.
dma_regs->csdp = 0x0a01;
dma_regs->ccr = 0x1000 | audio_state.output_dma; // source auto increment, don't enable yet
dma_regs->cicr = 0x0b;
dma_regs->cdsa_l = ((OMAP1510_MCBSP1_BASE + 0x806) & 0xffff); //McBSP1 DXR1
dma_regs->cdsa_u = ((OMAP1510_MCBSP1_BASE + 0x806) >> 16);
dma_regs->cfn = 0x1;
omap_dma_setup(audio_state.output_dma, eDmaOut);
// Initialize McBSP channel
outw(0x0000, OMAP1510_MCBSP1_BASE + 0x80a); // SPCR1
outw(0x0000, OMAP1510_MCBSP1_BASE + 0x808); // SPCR2
outw(0x0f03, OMAP1510_MCBSP1_BASE + 0x824); // PCR0
outw(0x0040, OMAP1510_MCBSP1_BASE + 0x80e); // RCR1
outw(0x8045, OMAP1510_MCBSP1_BASE + 0x80c); // RCR2
outw(0x0040, OMAP1510_MCBSP1_BASE + 0x812); // XCR1
outw(0x8041, OMAP1510_MCBSP1_BASE + 0x810); // XCR2
outw(0x0f0b, OMAP1510_MCBSP1_BASE + 0x816); // SRGR1
outw(0x101f, OMAP1510_MCBSP1_BASE + 0x814); // SRGR2
outw(0x0001, OMAP1510_MCBSP1_BASE + 0x80a); // SPCR1 enable
outw(0x03f1, OMAP1510_MCBSP1_BASE + 0x808); // SPCR2 enable
#endif
/* Wait for the UDA1341 to wake up */
mdelay(1);
/* external clock configuration */
omap1510_set_samplerate(audio_samplerate);
/* Initialize the UDA1341 internal state */
l3_open(&uda1341);
}
