static void __init htcherald_lcd_init(void)
{
u32 reg;
unsigned int tries = 200;
/* disable controller if active */
reg = omap_readl(OMAP_LCDC_CONTROL);
if (reg & OMAP_LCDC_CTRL_LCD_EN) {
reg &= ~OMAP_LCDC_CTRL_LCD_EN;
omap_writel(reg, OMAP_LCDC_CONTROL);
/* wait for end of frame */
while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)) {
tries--;
if (!tries)
break;
}
if (!tries)
printk(KERN_WARNING "Timeout waiting for end of frame "
"-- LCD may not be available\n");
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
reg &= ~(1 << 7);
omap_writew(reg, OMAP_DMA_LCD_CCR);
reg = omap_readw(OMAP_DMA_LCD_CTRL);
reg &= ~(1 << 8);
omap_writew(reg, OMAP_DMA_LCD_CTRL);
}
}
static void __init omap_nokia770_init_irq(void)
{
/* On Nokia 770, the SleepX signal is masked with an
* MPUIO line by default. It has to be unmasked for it
* to become functional */
/* SleepX mask direction */
omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
/* Unmask SleepX signal */
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
omap1_init_common_hw();
omap1_init_irq();
}
int
ck_set_input(ck_t ck, ck_t input)
{
int ret = 0, shift;
unsigned short reg;
unsigned long flags;
if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) {
ret = -EINVAL;
goto exit;
}
reg = omap_readw(CK_SELECT_REG(ck));
shift = CK_SELECT_SHIFT(ck);
spin_lock_irqsave(&clock_lock, flags);
if (input == OMAP_CLKIN) {
reg &= ~(1 << shift);
omap_writew(reg, CK_SELECT_REG(ck));
goto exit;
} else if (input == CK_PARENT(ck)) {
reg |= (1 << shift);
omap_writew(reg, CK_SELECT_REG(ck));
goto exit;
}
ret = -EINVAL;
exit:
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
static int __init omap_init_lcd_dma(void)
{
int r;
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
return r;
}
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!cpu_is_omap15xx()) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!cpu_is_omap15xx()) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
int
ck_get_input(ck_t ck, ck_t * input)
{
int ret = -EINVAL;
unsigned long flags;
if (!CK_IN_RANGE(ck))
goto exit;
ret = 0;
spin_lock_irqsave(&clock_lock, flags);
if (CK_CAN_SWITCH(ck)) {
int shift;
unsigned short reg;
reg = omap_readw(CK_SELECT_REG(ck));
shift = CK_SELECT_SHIFT(ck);
if (reg & (1 << shift)) {
*input = CK_PARENT(ck);
goto exit;
}
}
*input = OMAP_CLKIN;
exit:
spin_unlock_irqrestore(&clock_lock, flags);
return ret;
}
static int
__ck_set_pll_rate(ck_t ck, int rate)
{
unsigned short pll;
unsigned long flags;
if ((rate < 0) || (rate > CK_MAX_PLL_FREQ))
return -EINVAL;
/* Scan downward for the closest matching frequency */
while (rate && !test_bit(rate, (unsigned long *)&ck_valid_table))
rate--;
if (!rate) {
printk(KERN_ERR "%s: couldn't find a matching rate\n",
__FUNCTION__);
return -EINVAL;
}
spin_lock_irqsave(&clock_lock, flags);
pll = omap_readw(CK_RATE_REG(ck));
/* Clear the rate bits */
pll &= ~(0x1f << 5);
/* Set the rate bits */
pll |= (ck_lookup_table[rate - 1] << 5);
omap_writew(pll, CK_RATE_REG(ck));
spin_unlock_irqrestore(&clock_lock, flags);
return 0;
}
static irqreturn_t omap_otg_irq(int irq, void *arg)
{
u16 otg_irq;
otg_irq = omap_readw(OTG_IRQ_SRC);
if (otg_irq & OPRT_CHG) {
omap_writew(OPRT_CHG, OTG_IRQ_SRC);
} else if (otg_irq & B_SRP_TMROUT) {
omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
} else if (otg_irq & B_HNP_FAIL) {
omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
} else if (otg_irq & A_SRP_DETECT) {
omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
} else if (otg_irq & A_REQ_TMROUT) {
omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
} else if (otg_irq & A_VBUS_ERR) {
omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
} else if (otg_irq & DRIVER_SWITCH) {
#ifdef CONFIG_USB_OTG
if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
/* role is host */
usb_bus_start_enum(tu->otg.host,
tu->otg.host->otg_port);
}
#endif
omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
} else
return IRQ_NONE;
return IRQ_HANDLED;
}
int
ck_disable(ck_t ck)
{
unsigned short reg;
int ret = -EINVAL, shift;
unsigned long flags;
if (!CK_IN_RANGE(ck))
goto exit;
if (ck_debug)
printk(KERN_DEBUG "%s: %s\n", __FUNCTION__, CK_NAME(ck));
if (!CK_CAN_DISABLE(ck))
goto exit;
ret = 0;
if (ck == OMAP_CLKIN)
return -EINVAL;
spin_lock_irqsave(&clock_lock, flags);
reg = omap_readw(CK_ENABLE_REG(ck));
shift = CK_ENABLE_SHIFT(ck);
reg &= ~(1 << shift);
omap_writew(reg, CK_ENABLE_REG(ck));
spin_unlock_irqrestore(&clock_lock, flags);
exit:
return ret;
}
int omap_lcd_dma_running(void)
{
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap15xx())
if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
return 1;
return 0;
}
static int omap_mux_disable_wakeup(const char *muxname)
{
u16 val = 0;
val = omap_readw(CA_WAKE_MUX_REG);
val &= ~OMAP44XX_PADCONF_WAKEUPENABLE0;
omap_writew(val, CA_WAKE_MUX_REG);
return 0;
}
void __init mapphone_padconf_init(void)
{
int i;
#ifdef CONFIG_ARM_OF
mux_setting_init();
#endif
touch_int_fix();
for (i = 0; i < ARRAY_SIZE(padconf_settings); i++) {
if (is_omap343x_padconf_register(padconf_settings[i].offset)) {
unsigned long addr = padconf_settings[i].offset
+ OMAP343X_CTRL_BASE;
/*
despite the w, omap_readw actual reads a short which
is a half word on this architecture
*/
unsigned short val = omap_readw(addr);
#ifdef CONFIG_EMU_UART_DEBUG
if (is_emu_uart_iomux_reg(padconf_settings[i].offset)) {
printk(KERN_ERR "padconf ignored, offset = 0x%04x\n",
padconf_settings[i].offset);
continue;
}
#endif
val &= ~(OMAP343X_PADCONF_SETTING_MASK);
val |= padconf_settings[i].setting;
/* the SIM mux settings are for OMAP3430 */
if ((padconf_settings[i].offset == 0x150) ||
(padconf_settings[i].offset == 0x152) ||
(padconf_settings[i].offset == 0x154) ||
(padconf_settings[i].offset == 0x156)) {
if (cpu_is_omap3630())
continue;
}
/* the SIM mux settings are for OMAP3630 */
if ((padconf_settings[i].offset == 0xa54) ||
(padconf_settings[i].offset == 0xa56) ||
(padconf_settings[i].offset == 0xa58) ||
(padconf_settings[i].offset == 0xa5a)) {
if (cpu_is_omap3430())
continue;
}
omap_writew(val, addr);
} else {
printk(KERN_ERR "padconf check failed, offset = 0x%04x\n",
padconf_settings[i].offset);
}
}
return;
}
static int aat2862_suspend(struct i2c_client *client, pm_message_t state)
{
//printk(KERN_INFO"%s: new state: %d\n",__func__, state.event);
// 20100630 [email protected] Hub touchscreen power sequence [START_LGE]
aat2862_touch_ldo_enable(client, 0);
// 20100630 [email protected] Hub touchscreen power sequence [END_LGE]
// 20101016 [email protected] Turn off unnecessary modules upon BL off [START_LGE]
#if 0 // Followings reduces around 20uA.
gpio_direction_output(MY_HDMI_REG_EN, 0);
gpio_set_value(MY_HDMI_REG_EN, 0);
gpio_direction_output(MY_CAM_SUBPM_EN, 0);
gpio_set_value(MY_CAM_SUBPM_EN, 0);
gpio_direction_output(MY_CAM_VCM_EN, 0);
gpio_set_value(MY_CAM_VCM_EN, 0);
gpio_direction_output(MY_DMB_EN, 0);
gpio_set_value(MY_DMB_EN, 0);
gpio_direction_output(MY_MOTION_INT, 0);
gpio_direction_output(MY_COM_INT, 0);
#endif
#if 0 // Followings reduces around 60uA.
i2c3_scl = omap_readw(0x480021C2); // sookyoung.kim
i2c3_sda = omap_readw(0x480021C4); // sookyoung.kim
omap_writew(0x0000, 0x480021C2); // sookyoung.kim
omap_writew(0x0000, 0x480021C4); // sookyoung.kim
#endif
#if 0 // Followings, coupled with memory refresh rate control, reduces around 600uA.
i2c4_scl = omap_readw(0x48002A00); // sookyoung.kim
i2c4_sda = omap_readw(0x48002A02); // sookyoung.kim
omap_writew(0x0000, 0x48002A00); // sookyoung.kim
omap_writew(0x0000, 0x48002A02); // sookyoung.kim
#endif
// 20101016 [email protected] Turn off unnecessary modules upon BL off [END_LGE]
client->dev.power.power_state = state;
aat2862_write_reg(client, 0x02, 0x00);
gpio_direction_output(MY_LCD_CP_EN, 0);
gpio_set_value(MY_LCD_CP_EN, 0);
return 0;
}
static void __init htcoxygen_usb_otg(void)
{
/* clock configuration */
omap_writew(omap_readw(ULPD_SOFT_REQ) | (1 << 8) | SOFT_USB_CLK_REQ, ULPD_SOFT_REQ);
// clk_enable(&l3_ocpi_ck);
omap_writew(omap_readw(ARM_IDLECT3) | (1 << 0), ARM_IDLECT3);
/* pin muxing */
omap_writel(omap_readl(OMAP730_MODE_1) & ~(1 << 2), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) & ~(1 << 3), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) | (1 << 15), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) | (1 << 23), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) | (1 << 26), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) | (1 << 25), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) & ~(1 << 24), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) & ~(1 << 10), OMAP730_MODE_1);
omap_writel(omap_readl(OMAP730_MODE_1) & ~(1 << 11), OMAP730_MODE_1);
}
static void write_omap_mux_register(u16 offset, u8 mode, u8 input_en)
{
u16 tmp_val, reg_val;
u32 reg = OMAP343X_CTRL_BASE + offset;
reg_val = mode | (input_en << 8) | 0x0018;
tmp_val = omap_readw(reg) & ~(0x0007 | (1 << 8) | 0x0018);
reg_val = reg_val | tmp_val;
omap_writew(reg_val, reg);
}
static void htcoxygen_lcd_init(void)
{
u32 reg;
/* disable controller if active */
reg = omap_readl(OMAP_LCDC_CONTROL);
if (reg & OMAP_LCDC_CTRL_LCD_EN) {
reg &= ~OMAP_LCDC_CTRL_LCD_EN;
omap_writel(reg, OMAP_LCDC_CONTROL);
/* wait for end of frame */
while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE));
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
reg &= ~(1 << 7);
omap_writew(reg, OMAP_DMA_LCD_CCR);
reg = omap_readw(OMAP_DMA_LCD_CTRL);
reg &= ~(1 << 8);
omap_writew(reg, OMAP_DMA_LCD_CTRL);
}
}
static void __init omap_nokia770_init(void)
{
/* On Nokia 770, the SleepX signal is masked with an
* MPUIO line by default. It has to be unmasked for it
* to become functional */
/* SleepX mask direction */
omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
/* Unmask SleepX signal */
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
spi_register_board_info(nokia770_spi_board_info,
ARRAY_SIZE(nokia770_spi_board_info));
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
hwa742_dev_init();
ads7846_dev_init();
mipid_dev_init();
omap1_usb_init(&nokia770_usb_config);
nokia770_mmc_init();
}
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
void omap1_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
omap_writew(1, ARM_RSTCT1);
}
static int
__ck_get_clkm_rate(ck_t ck)
{
static int bits2div[] = { 1, 2, 4, 8 };
int in, bits, reg, shift;
reg = omap_readw(CK_RATE_REG(ck));
shift = CK_RATE_SHIFT(ck);
in = ck_get_rate(CK_PARENT(ck));
bits = (reg & (3 << shift)) >> shift;
return (in / bits2div[bits]);
}
static int
__ck_get_pll_rate(ck_t ck)
{
int m, d;
unsigned short pll = omap_readw(CK_RATE_REG(ck));
m = (pll & (0x1f << 7)) >> 7;
m = m ? m : 1;
d = (pll & (3 << 5)) >> 5;
d++;
return ((source_clock * m) / d);
}
static u_char ams_delta_read_byte(struct mtd_info *mtd)
{
u_char res;
struct nand_chip *this = mtd->priv;
ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE, 0);
ndelay(40);
omap_writew(~0, (OMAP_MPUIO_BASE + OMAP_MPUIO_IO_CNTL));
res = omap_readw(this->IO_ADDR_R);
ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE,
AMS_DELTA_LATCH2_NAND_NRE);
return res;
}
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!cpu_is_omap15xx())
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
static void __init omap_fsample_init(void)
{
omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
OMAP7XX_IO_CONF_9);
fsample_init_smc91x();
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
omap_cfg_reg(E2_7XX_KBR0);
omap_cfg_reg(J7_7XX_KBR1);
omap_cfg_reg(E1_7XX_KBR2);
omap_cfg_reg(F3_7XX_KBR3);
omap_cfg_reg(D2_7XX_KBR4);
omap_cfg_reg(C2_7XX_KBC0);
omap_cfg_reg(D3_7XX_KBC1);
omap_cfg_reg(E4_7XX_KBC2);
omap_cfg_reg(F4_7XX_KBC3);
omap_cfg_reg(E3_7XX_KBC4);
platform_add_devices(devices, ARRAY_SIZE(devices));
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
omapfb_set_lcd_config(&fsample_lcd_config);
}
/*
* Check if bootloader / platform code has configured the SDI pads properly.
* This means it either configured all required pads for SDI mode, or that it
* left all the required pads unconfigured.
*/
static int sdi_pad_init(struct omap_display *display)
{
unsigned req_map;
bool configured = false;
bool unconfigured = false;
int data_pairs;
int i;
data_pairs = display->hw_config.u.sdi.datapairs;
req_map = (1 << (data_pairs * 2)) - 1; /* data lanes */
req_map |= 3 << 6; /* clk lane */
for (i = 0; i < ARRAY_SIZE(sdi_pads); i++) {
u32 reg;
u32 val;
if (!((1 << i) & req_map))
/* Ignore unneded pads. */
continue;
reg = CONTROL_PADCONF_BASE + sdi_pads[i];
val = omap_readw(reg);
switch (val & 0x07) { /* pad mode */
case 1:
if (unconfigured)
break;
/* Is the pull configuration ok for SDI mode? */
if ((val & OMAP_SDI_PAD_MASK) != OMAP_SDI_PAD_EN)
break;
configured = true;
break;
case 0:
case 7:
if (configured)
break;
unconfigured = true;
break;
default:
break;
}
}
if (i != ARRAY_SIZE(sdi_pads)) {
DSSERR("SDI: invalid pad configuration\n");
return -1;
}
return 0;
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
static void __init ams_delta_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
/* parallel camera interface */
omap_cfg_reg(H19_1610_CAM_EXCLK);
omap_cfg_reg(J15_1610_CAM_LCLK);
omap_cfg_reg(L18_1610_CAM_VS);
omap_cfg_reg(L15_1610_CAM_HS);
omap_cfg_reg(L19_1610_CAM_D0);
omap_cfg_reg(K14_1610_CAM_D1);
omap_cfg_reg(K15_1610_CAM_D2);
omap_cfg_reg(K19_1610_CAM_D3);
omap_cfg_reg(K18_1610_CAM_D4);
omap_cfg_reg(J14_1610_CAM_D5);
omap_cfg_reg(J19_1610_CAM_D6);
omap_cfg_reg(J18_1610_CAM_D7);
iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
omap_board_config = ams_delta_config;
omap_board_config_size = ARRAY_SIZE(ams_delta_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
/* Clear latch2 (NAND, LCD, modem enable) */
ams_delta_latch2_write(~0, 0);
omap1_usb_init(&ams_delta_usb_config);
omap1_set_camera_info(&ams_delta_camera_platform_data);
#ifdef CONFIG_LEDS_TRIGGERS
led_trigger_register_simple("ams_delta_camera",
&ams_delta_camera_led_trigger);
#endif
platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
#ifdef CONFIG_AMS_DELTA_FIQ
ams_delta_init_fiq();
#endif
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
}
static void __init ams_delta_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
omap_board_config = ams_delta_config;
omap_board_config_size = ARRAY_SIZE(ams_delta_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
/* Clear latch2 (NAND, LCD, modem enable) */
ams_delta_latch2_write(~0, 0);
omap_usb_init(&ams_delta_usb_config);
platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
}
static void __init omap_perseus2_map_io(void)
{
omap_map_io();
iotable_init(omap_perseus2_io_desc,
ARRAY_SIZE(omap_perseus2_io_desc));
/* Early, board-dependent init */
/*
* Hold GSM Reset until needed
*/
omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
/*
* UARTs -> done automagically by 8250 driver
*/
/*
* CSx timings, GPIO Mux ... setup
*/
/* Flash: CS0 timings setup */
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
/*
* Ethernet support trough the debug board
* CS1 timings setup
*/
omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
omap_serial_init(p2_serial_ports);
}
