void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, struct videomode *vm) { u32 timing_h = 0; u32 timing_v = 0; unsigned hsync_len_offset = 1; DSSDBG("Enter hdmi_wp_video_config_timing\n"); /* * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1. * However, we don't support OMAP5 ES1 at all, so we can just check for * OMAP4 here. */ if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || omapdss_get_version() == OMAPDSS_VER_OMAP4) hsync_len_offset = 0; timing_h |= FLD_VAL(vm->hback_porch, 31, 20); timing_h |= FLD_VAL(vm->hfront_porch, 19, 8); timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); timing_v |= FLD_VAL(vm->vback_porch, 31, 20); timing_v |= FLD_VAL(vm->vfront_porch, 19, 8); timing_v |= FLD_VAL(vm->vsync_len, 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); }
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, struct omap_video_timings *timings) { u32 timing_h = 0; u32 timing_v = 0; bool hsw_minus_one = true; DSSDBG("Enter hdmi_wp_video_config_timing\n"); /* * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1. * However, we don't support OMAP5 ES1 at all, so we can just check for * OMAP4 here. */ if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || omapdss_get_version() == OMAPDSS_VER_OMAP4) hsw_minus_one = false; timing_h |= FLD_VAL(timings->hbp, 31, 20); timing_h |= FLD_VAL(timings->hfp, 19, 8); timing_h |= FLD_VAL(timings->hsw - (hsw_minus_one ? 1 : 0), 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); timing_v |= FLD_VAL(timings->vbp, 31, 20); timing_v |= FLD_VAL(timings->vfp, 19, 8); timing_v |= FLD_VAL(timings->vsw, 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); }
static int __init omap_dss_probe(struct platform_device *pdev) { struct omap_dss_board_info *pdata = pdev->dev.platform_data; int r; core.pdev = pdev; dss_features_init(omapdss_get_version()); r = dss_initialize_debugfs(); if (r) goto err_debugfs; if (def_disp_name) core.default_display_name = def_disp_name; else if (pdata->default_display_name) core.default_display_name = pdata->default_display_name; else if (pdata->default_device) core.default_display_name = pdata->default_device->name; register_pm_notifier(&omap_dss_pm_notif_block); return 0; err_debugfs: return r; }
static int hdmi_pll_init_features(struct platform_device *pdev) { struct hdmi_pll_features *dst; const struct hdmi_pll_features *src; dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); if (!dst) { dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n"); return -ENOMEM; } switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP4430_ES1: case OMAPDSS_VER_OMAP4430_ES2: case OMAPDSS_VER_OMAP4: src = &omap44xx_pll_feats; break; case OMAPDSS_VER_OMAP5: src = &omap54xx_pll_feats; break; default: return -ENODEV; } memcpy(dst, src, sizeof(*dst)); pll_feat = dst; return 0; }
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, struct hdmi_audio_format *aud_fmt) { u32 r; DSSDBG("Enter hdmi_wp_audio_config_format\n"); r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || omapdss_get_version() == OMAPDSS_VER_OMAP4) { r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); } r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); r = FLD_MOD(r, aud_fmt->type, 4, 4); r = FLD_MOD(r, aud_fmt->justification, 3, 3); r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); }
static const struct hdmi_phy_features *hdmi_phy_get_features(void) { switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP4430_ES1: case OMAPDSS_VER_OMAP4430_ES2: case OMAPDSS_VER_OMAP4: return &omap44xx_phy_feats; case OMAPDSS_VER_OMAP5: case OMAPDSS_VER_DRA7xx: return &omap54xx_phy_feats; default: return NULL; } }
static struct platform_device *dpi_get_dsidev(enum omap_channel channel) { /* * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL * would also be used for DISPC fclk. Meaning, when the DPI output is * disabled, DISPC clock will be disabled, and TV out will stop. */ switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP24xx: case OMAPDSS_VER_OMAP34xx_ES1: case OMAPDSS_VER_OMAP34xx_ES3: case OMAPDSS_VER_OMAP3630: case OMAPDSS_VER_AM35xx: case OMAPDSS_VER_AM43xx: return NULL; case OMAPDSS_VER_OMAP4430_ES1: case OMAPDSS_VER_OMAP4430_ES2: case OMAPDSS_VER_OMAP4: switch (channel) { case OMAP_DSS_CHANNEL_LCD: return dsi_get_dsidev_from_id(0); case OMAP_DSS_CHANNEL_LCD2: return dsi_get_dsidev_from_id(1); default: return NULL; } case OMAPDSS_VER_OMAP5: switch (channel) { case OMAP_DSS_CHANNEL_LCD: return dsi_get_dsidev_from_id(0); case OMAP_DSS_CHANNEL_LCD3: return dsi_get_dsidev_from_id(1); default: return NULL; } default: return NULL; } }
static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll) { struct dss_pll *pll = &hpll->pll; struct clk *clk; int r; clk = devm_clk_get(&pdev->dev, "sys_clk"); if (IS_ERR(clk)) { DSSERR("can't get sys_clk\n"); return PTR_ERR(clk); } pll->name = "hdmi"; pll->id = DSS_PLL_HDMI; pll->base = hpll->base; pll->clkin = clk; switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP4430_ES1: case OMAPDSS_VER_OMAP4430_ES2: case OMAPDSS_VER_OMAP4: pll->hw = &dss_omap4_hdmi_pll_hw; break; case OMAPDSS_VER_OMAP5: case OMAPDSS_VER_DRA7xx: pll->hw = &dss_omap5_hdmi_pll_hw; break; default: return -ENODEV; } pll->ops = &dsi_pll_ops; r = dss_pll_register(pll); if (r) return r; return 0; }
/* * Return a hardcoded channel for the DPI output. This should work for * current use cases, but this can be later expanded to either resolve * the channel in some more dynamic manner, or get the channel as a user * parameter. */ static enum omap_channel dpi_get_channel(void) { switch (omapdss_get_version()) { case OMAPDSS_VER_OMAP24xx: case OMAPDSS_VER_OMAP34xx_ES1: case OMAPDSS_VER_OMAP34xx_ES3: case OMAPDSS_VER_OMAP3630: case OMAPDSS_VER_AM35xx: return OMAP_DSS_CHANNEL_LCD; case OMAPDSS_VER_OMAP4430_ES1: case OMAPDSS_VER_OMAP4430_ES2: case OMAPDSS_VER_OMAP4: return OMAP_DSS_CHANNEL_LCD2; case OMAPDSS_VER_OMAP5: return OMAP_DSS_CHANNEL_LCD3; default: DSSWARN("unsupported DSS version\n"); return OMAP_DSS_CHANNEL_LCD; } }
static int __init hdmi_init_display(struct omap_dss_device *dssdev) { int r; struct gpio gpios[] = { { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" }, { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" }, { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" }, }; DSSDBG("init_display\n"); dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version()); if (hdmi.vdda_hdmi_dac_reg == NULL) { struct regulator *reg; reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac"); /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */ if (IS_ERR(reg)) reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC"); if (IS_ERR(reg)) { DSSERR("can't get VDDA_HDMI_DAC regulator\n"); return PTR_ERR(reg); } hdmi.vdda_hdmi_dac_reg = reg; } r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); if (r) return r; return 0; }