/******************************************************************************* * This function passes control to the OPTEE image (BL32) for the first time * on the primary cpu after a cold boot. It assumes that a valid secure * context has already been created by opteed_setup() which can be directly * used. It also assumes that a valid non-secure context has been * initialised by PSCI so it does not need to save and restore any * non-secure state. This function performs a synchronous entry into * OPTEE. OPTEE passes control back to this routine through a SMC. ******************************************************************************/ static int32_t opteed_init(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; entry_point_info_t *optee_entry_point; uint64_t rc; /* * Get information about the OPTEE (BL32) image. Its * absence is a critical failure. */ optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); assert(optee_entry_point); cm_init_context(mpidr, optee_entry_point); /* * Arrange for an entry into OPTEE. It will be returned via * OPTEE_ENTRY_DONE case */ rc = opteed_synchronous_sp_entry(optee_ctx); assert(rc != 0); return rc; }
/******************************************************************************* * This cpu has been turned on. Enter OPTEE to initialise S-EL1 and other bits * before passing control back to the Secure Monitor. Entry in S-El1 is done * after initialising minimal architectural state that guarantees safe * execution. ******************************************************************************/ static void opteed_cpu_on_finish_handler(uint64_t unused) { int32_t rc = 0; uint32_t linear_id = plat_my_core_pos(); optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; entry_point_info_t optee_on_entrypoint; assert(optee_vectors); assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF); opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw, (uint64_t)&optee_vectors->cpu_on_entry, 0, 0, 0, optee_ctx); /* Initialise this cpu's secure context */ cm_init_my_context(&optee_on_entrypoint); /* Enter OPTEE */ rc = opteed_synchronous_sp_entry(optee_ctx); /* * Read the response from OPTEE. A non-zero return means that * something went wrong while communicating with OPTEE. */ if (rc != 0) panic(); /* Update its context to reflect the state OPTEE is in */ set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); }
/******************************************************************************* * This cpu is being turned off. Allow the OPTEED/OPTEE to perform any actions * needed ******************************************************************************/ static int32_t opteed_cpu_off_handler(uint64_t unused) { int32_t rc = 0; uint32_t linear_id = plat_my_core_pos(); optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; assert(optee_vectors); assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); /* Program the entry point and enter OPTEE */ cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_off_entry); rc = opteed_synchronous_sp_entry(optee_ctx); /* * Read the response from OPTEE. A non-zero return means that * something went wrong while communicating with OPTEE. */ if (rc != 0) panic(); /* * Reset OPTEE's context for a fresh start when this cpu is turned on * subsequently. */ set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); return 0; }
/******************************************************************************* * This cpu has resumed from suspend. The OPTEED saved the OPTEE context when it * completed the preceding suspend call. Use that context to program an entry * into OPTEE to allow it to do any remaining book keeping ******************************************************************************/ static void opteed_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) { int32_t rc = 0; uint32_t linear_id = plat_my_core_pos(); optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; assert(optee_vectors); assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND); /* Program the entry point, max_off_pwrlvl and enter the SP */ write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), CTX_GPREG_X0, max_off_pwrlvl); cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry); rc = opteed_synchronous_sp_entry(optee_ctx); /* * Read the response from OPTEE. A non-zero return means that * something went wrong while communicating with OPTEE. */ if (rc != 0) panic(); /* Update its context to reflect the state OPTEE is in */ set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); }
/******************************************************************************* * System is about to be reset. Allow the OPTEED/OPTEE to perform * any actions needed. ******************************************************************************/ static void opteed_system_reset(void) { uint32_t linear_id = plat_my_core_pos(); optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; assert(optee_vectors); assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); /* Program the entry point */ cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_reset_entry); /* Enter OPTEE. We do not care about the return value because we * must continue the reset anyway */ opteed_synchronous_sp_entry(optee_ctx); }