static void xonar_d1_init(struct oxygen *chip) { struct xonar_cs43xx *data = chip->model_data; data->generic.anti_pop_delay = 800; data->generic.output_enable_bit = GPIO_D1_OUTPUT_ENABLE; data->cs4398_regs[2] = CS4398_FM_SINGLE | CS4398_DEM_NONE | CS4398_DIF_LJUST; data->cs4398_regs[4] = CS4398_MUTEP_LOW | CS4398_MUTE_B | CS4398_MUTE_A | CS4398_PAMUTE; data->cs4398_regs[5] = 60 * 2; data->cs4398_regs[6] = 60 * 2; data->cs4398_regs[7] = CS4398_RMP_DN | CS4398_RMP_UP | CS4398_ZERO_CROSS | CS4398_SOFT_RAMP; data->cs4362a_regs[4] = CS4362A_RMP_DN | CS4362A_DEM_NONE; data->cs4362a_regs[6] = CS4362A_FM_SINGLE | CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L; data->cs4362a_regs[7] = 60 | CS4362A_MUTE; data->cs4362a_regs[8] = 60 | CS4362A_MUTE; data->cs4362a_regs[9] = data->cs4362a_regs[6]; data->cs4362a_regs[10] = 60 | CS4362A_MUTE; data->cs4362a_regs[11] = 60 | CS4362A_MUTE; data->cs4362a_regs[12] = data->cs4362a_regs[6]; data->cs4362a_regs[13] = 60 | CS4362A_MUTE; data->cs4362a_regs[14] = 60 | CS4362A_MUTE; oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_FAST); cs43xx_registers_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D1_FRONT_PANEL | GPIO_D1_INPUT_ROUTE); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_D1_FRONT_PANEL | GPIO_D1_INPUT_ROUTE); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_FMIC2MIC); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "CS4398"); snd_component_add(chip->card, "CS4362A"); snd_component_add(chip->card, "CS5361"); }
static void xonar_common_init(struct oxygen *chip) { struct xonar_data *data = chip->model_data; if (data->ext_power_reg) { oxygen_set_bits8(chip, data->ext_power_int_reg, data->ext_power_bit); chip->interrupt_mask |= OXYGEN_INT_GPIO; chip->model.gpio_changed = xonar_gpio_changed; data->has_power = !!(oxygen_read8(chip, data->ext_power_reg) & data->ext_power_bit); } oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CS53x1_M_MASK | data->output_enable_bit); oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, GPIO_CS53x1_M_SINGLE, GPIO_CS53x1_M_MASK); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_FMIC2MIC); xonar_enable_output(chip); }
static void xonar_d2_init(struct oxygen *chip) { struct xonar_pcm179x *data = chip->model_data; data->generic.anti_pop_delay = 300; data->generic.output_enable_bit = GPIO_D2_OUTPUT_ENABLE; data->dacs = 4; pcm1796_init(chip); oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_D2_ALT); oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_D2_ALT); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_FMIC2MIC); xonar_init_cs53x1(chip); xonar_enable_output(chip); snd_component_add(chip->card, "PCM1796"); snd_component_add(chip->card, "CS5381"); }
static void oxygen_init(struct oxygen *chip) { unsigned int i; chip->dac_routing = 1; for (i = 0; i < 8; ++i) chip->dac_volume[i] = chip->model.dac_volume_min; chip->dac_mute = 1; chip->spdif_playback_enable = 1; chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); chip->spdif_pcm_bits = chip->spdif_bits; if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2) chip->revision = 2; else chip->revision = 1; if (chip->revision == 1) oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_PCI_MEM_W_1_CLOCK); i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; oxygen_write8_masked(chip, OXYGEN_FUNCTION, OXYGEN_FUNCTION_RESET_CODEC | chip->model.function_flags, OXYGEN_FUNCTION_RESET_CODEC | OXYGEN_FUNCTION_2WIRE_SPI_MASK | OXYGEN_FUNCTION_ENABLE_SPI_4_5); oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, OXYGEN_PLAY_CHANNELS_2 | OXYGEN_DMA_A_BURST_8 | OXYGEN_DMA_MULTICH_BURST_8); oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); oxygen_write8_masked(chip, OXYGEN_MISC, chip->model.misc_flags, OXYGEN_MISC_WRITE_PCI_SUBID | OXYGEN_MISC_REC_C_FROM_SPDIF | OXYGEN_MISC_REC_B_FROM_AC97 | OXYGEN_MISC_REC_A_FROM_MULTICH | OXYGEN_MISC_MIDI); oxygen_write8(chip, OXYGEN_REC_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); oxygen_write8(chip, OXYGEN_PLAY_FORMAT, (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, OXYGEN_RATE_48000 | chip->model.dac_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | CAPTURE_2_FROM_I2S_2)) oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_RATE_48000 | chip->model.adc_i2s_format | OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); else oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_OUT_ENABLE | OXYGEN_SPDIF_LOOPBACK); if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_96, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK | OXYGEN_SPDIF_SENSE_PAR | OXYGEN_SPDIF_LOCK_PAR | OXYGEN_SPDIF_IN_CLOCK_MASK); else oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_SENSE_MASK | OXYGEN_SPDIF_LOCK_MASK | OXYGEN_SPDIF_RATE_MASK); oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, OXYGEN_2WIRE_LENGTH_8 | OXYGEN_2WIRE_INTERRUPT_MASK | OXYGEN_2WIRE_SPEED_STANDARD); oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); oxygen_write16(chip, OXYGEN_PLAY_ROUTING, OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF | (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); oxygen_write8(chip, OXYGEN_REC_ROUTING, OXYGEN_REC_A_ROUTE_I2S_ADC_1 | OXYGEN_REC_B_ROUTE_I2S_ADC_2 | OXYGEN_REC_C_ROUTE_SPDIF); oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); if (chip->has_ac97_0 | chip->has_ac97_1) oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, OXYGEN_AC97_INT_READ_DONE | OXYGEN_AC97_INT_WRITE_DONE); else oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); if (!(chip->has_ac97_0 | chip->has_ac97_1)) oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_CLOCK_DISABLE); if (!chip->has_ac97_0) { oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, OXYGEN_AC97_NO_CODEC_0); } else { oxygen_write_ac97(chip, 0, AC97_RESET, 0); msleep(1); oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, CM9780_GPIO0IO | CM9780_GPIO1IO); oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, CM9780_BSTSEL | CM9780_STRO_MIC | CM9780_MIX2FR | CM9780_PCBSW); oxygen_ac97_set_bits(chip, 0, CM9780_JACK, CM9780_RSOE | CM9780_CBOE | CM9780_SSOE | CM9780_FROE | CM9780_MIC2MIC | CM9780_LI2LI); oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, CM9780_GPO0); /* power down unused ADCs and DACs */ oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, AC97_PD_PR0 | AC97_PD_PR1); oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); } if (chip->has_ac97_1) { oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, OXYGEN_AC97_CODEC1_SLOT3 | OXYGEN_AC97_CODEC1_SLOT4); oxygen_write_ac97(chip, 1, AC97_RESET, 0); msleep(1); oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); } }