static void enable_clock_gating(pci_dev_t dev) { u32 reg32; u16 reg16; setbits_le32(RCB_REG(0x2234), 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); reg32 = readl(RCB_REG(CG)); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 16); reg32 |= (1 << 17); reg32 |= (1 << 18); reg32 |= (1 << 22); reg32 |= (1 << 23); reg32 &= ~(1 << 20); reg32 |= (1 << 19); reg32 |= (1 << 0); reg32 |= (0xf << 1); writel(reg32, RCB_REG(CG)); setbits_le32(RCB_REG(0x38c0), 0x7); setbits_le32(RCB_REG(0x36d4), 0x6680c004); setbits_le32(RCB_REG(0x3564), 0x3); }
static void enable_clock_gating(device_t dev) { u32 reg32; u16 reg16; RCBA32_AND_OR(0x2234, ~0UL, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 16); reg32 |= (1 << 17); reg32 |= (1 << 18); reg32 |= (1 << 22); reg32 |= (1 << 23); reg32 &= ~(1 << 20); reg32 |= (1 << 19); reg32 |= (1 << 0); reg32 |= (0xf << 1); RCBA32(CG) = reg32; RCBA32_OR(0x38c0, 0x7); RCBA32_OR(0x36d4, 0x6680c004); RCBA32_OR(0x3564, 0x3); }
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ static void serialio_init_once(int acpi_mode) { if (acpi_mode) { /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); } /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); }
/* Put Serial IO D23:F0 device into desired mode. */ static void serialio_d23_mode(int acpi_mode) { u32 portctrl = 0; /* Snoop select 1. */ pch_iobp_update(SIO_IOBP_PORTCTRL1, 0, SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1)); if (acpi_mode) { /* Enable ACPI interrupt mode. */ portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN; /* Disable PCI config space. */ portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS; } pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl); }
void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev; #else struct device *dev; #endif /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { case 0: dev = PCH_DEV_UART0; gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS; break; case 1: dev = PCH_DEV_UART1; gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS; break; default: return; } /* Program IOBP GPIODF */ pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf); /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ reg_script_run_on_dev(dev, uart_init); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ uart8250_mem_init(CONFIG_TTYS0_BASE, 1); }
static void usb_xhci_clock_gating(struct device *dev) { u32 reg32; u16 reg16; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ if (pch_is_lp()) { /* D20:F0:40h[18,17,8] = 111b */ reg32 |= (1 << 18) | (1 << 17) | (1 << 8); /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ reg32 &= ~(1 << 19); reg32 |= (1 << 21) | (1 << 20); } else { /* D20:F0:40h[21,20,18,17,8] = 11111b */ reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); } /* Avoid writing upper byte as it is write-once */ pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); /* D20:F0:44h[9,7,3] = 111b */ reg16 = pci_read_config16(dev, 0x44); reg16 |= (1 << 9) | (1 << 7) | (1 << 3); pci_write_config16(dev, 0x44, reg16); reg32 = pci_read_config32(dev, 0xa0); if (pch_is_lp()) { /* D20:F0:A0h[18] = 1 */ reg32 |= (1 << 18); } else { /* D20:F0:A0h[6] = 1 */ reg32 |= (1 << 6); } pci_write_config32(dev, 0xa0, reg32); /* D20:F0:A4h[13] = 0 */ reg32 = pci_read_config32(dev, 0xa4); reg32 &= ~(1 << 13); pci_write_config32(dev, 0xa4, reg32); }
static void usb_ehci_clock_gating(struct device *dev) { u32 reg32; /* IOBP 0xE5004001[7:6] = 11b */ pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); /* Dx:F0:DCh[5,2,1] = 111b * Dx:F0:DCh[0] = 1b when EHCI controller is disabled */ reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 5) | (1 << 2) | (1 << 1); pci_write_config32(dev, 0xdc, reg32); /* Dx:F0:78h[1:0] = 11b */ reg32 = pci_read_config32(dev, 0x78); reg32 |= (1 << 1) | (1 << 0); pci_write_config32(dev, 0x78, reg32); }
/* Put Serial IO D21:F0-F6 device into desired mode. */ static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) { u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; /* Snoop select 1. */ portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); /* Set interrupt pin. */ portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); if (acpi_mode) { /* Enable ACPI interrupt mode. */ portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; /* Disable PCI config space. */ portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS; } pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); }
static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch) { unsigned int port_map, speed_support, port_tx; const void *blob = gd->fdt_blob; int node = dev->of_offset; const char *mode; u32 reg32; u16 reg16; debug("SATA: Initializing...\n"); /* SATA configuration */ port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); speed_support = fdtdec_get_int(blob, node, "sata_interface_speed_support", 0); mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { u32 abar; debug("SATA: Controller in AHCI mode\n"); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); common_sata_init(dev, 0x8000 | port_map); /* Initialize AHCI memory-mapped space */ abar = dm_pci_read_bar32(dev, 5); debug("ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = readl(abar + 0x00); reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ /* Set ISS, if available */ if (speed_support) { reg32 &= ~0x00f00000; reg32 |= (speed_support & 0x03) << 20; } writel(reg32, abar + 0x00); /* PI (Ports implemented) */ writel(port_map, abar + 0x0c); (void) readl(abar + 0x0c); /* Read back 1 */ (void) readl(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = readl(abar + 0x24); reg32 &= ~0x00000002; writel(reg32, abar + 0x24); /* VSP (Vendor Specific Register */ reg32 = readl(abar + 0xa0); reg32 &= ~0x00000005; writel(reg32, abar + 0xa0); } else if (!strcmp(mode, "combined")) { debug("SATA: Controller in combined mode\n"); /* No AHCI: clear AHCI base */ dm_pci_write_bar32(dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; dm_pci_write_config16(dev, PCI_COMMAND, reg16); dm_pci_write_config8(dev, 0x09, 0x80); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); common_sata_init(dev, port_map); } else { debug("SATA: Controller in plain-ide mode\n"); /* No AHCI: clear AHCI base */ dm_pci_write_bar32(dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ dm_pci_read_config16(dev, PCI_COMMAND, ®16); reg16 &= ~PCI_COMMAND_MEMORY; dm_pci_write_config16(dev, PCI_COMMAND, reg16); /* * Native mode capable on both primary and secondary (0xa) * OR'ed with enabled (0x50) = 0xf */ dm_pci_write_config8(dev, 0x09, 0x8f); /* Set timings */ dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); common_sata_init(dev, port_map); } /* Set Gen3 Transmitter settings if needed */ port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); if (port_tx) pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx); port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0); if (port_tx) pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx); /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; reg32 |= 0x5555aa; sir_write(dev, 0x54, reg32); sir_write(dev, 0x64, 0xcccc8484); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0xcccc; sir_write(dev, 0x68, reg32); reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; reg32 |= 0x88880000; sir_write(dev, 0x78, reg32); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000); sir_write(dev, 0xc4, 0x0c0c0c0c); sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000); pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100); }
/* Set bit in Function Disble register to hide this device */ void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ RCBA32_OR(FD, PCH_DISABLE_ADSPD); break; case PCI_DEVFN(20, 0): /* XHCI */ RCBA32_OR(FD, PCH_DISABLE_XHCI); break; case PCI_DEVFN(21, 0): /* DMA */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 1): /* I2C0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 2): /* I2C1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 3): /* SPI0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 4): /* SPI1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 5): /* UART0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(21, 6): /* UART1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; case PCI_DEVFN(22, 1): /* MEI #2 */ RCBA32_OR(FD2, PCH_DISABLE_MEI2); break; case PCI_DEVFN(22, 2): /* IDE-R */ RCBA32_OR(FD2, PCH_DISABLE_IDER); break; case PCI_DEVFN(22, 3): /* KT */ RCBA32_OR(FD2, PCH_DISABLE_KT); break; case PCI_DEVFN(23, 0): /* SDIO */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ RCBA32_OR(BUC, PCH_DISABLE_GBE); break; case PCI_DEVFN(26, 0): /* EHCI #2 */ RCBA32_OR(FD, PCH_DISABLE_EHCI2); break; case PCI_DEVFN(27, 0): /* HD Audio Controller */ RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); break; case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); break; case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; case PCI_DEVFN(31, 0): /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; case PCI_DEVFN(31, 2): /* SATA #1 */ RCBA32_OR(FD, PCH_DISABLE_SATA1); break; case PCI_DEVFN(31, 3): /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; case PCI_DEVFN(31, 5): /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; case PCI_DEVFN(31, 6): /* Thermal Subsystem */ RCBA32_OR(FD, PCH_DISABLE_THERMAL); break; } }
static void sata_init(struct device *dev) { u32 reg32; u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); pci_write_config8(dev, 0x09, 0x80); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; /* 6 ports SKU + ORM */ reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ if (config->sata_interface_speed_support) { reg32 &= ~0x00f00000; reg32 |= (config->sata_interface_speed_support & 0x03) << 20; } write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); reg32 &= ~0x00000002; write32(abar + 0x24, reg32); /* VSP (Vendor Specific Register */ reg32 = read32(abar + 0xa0); reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf */ pci_write_config8(dev, 0x09, 0x8f); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) pch_iobp_update(SATA_IOBP_SP0G3IR, 0, config->sata_port0_gen3_tx); if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1G3IR, 0, config->sata_port1_gen3_tx); /* Additional Programming Requirements */ sir_write(dev, 0x04, 0x00001600); sir_write(dev, 0x28, 0xa0000033); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; reg32 |= 0x5555aa; sir_write(dev, 0x54, reg32); sir_write(dev, 0x64, 0xcccc8484); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0xcccc; sir_write(dev, 0x68, reg32); reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; reg32 |= 0x88880000; sir_write(dev, 0x78, reg32); sir_write(dev, 0x84, 0x001c7000); sir_write(dev, 0x88, 0x88338822); sir_write(dev, 0xa0, 0x001c7000); // a4 sir_write(dev, 0xc4, 0x0c0c0c0c); sir_write(dev, 0xc8, 0x0c0c0c0c); sir_write(dev, 0xd4, 0x10000000); pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000); pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100); }
static void sata_init(struct device *dev) { u32 reg32; u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; printk(BIOS_DEBUG, "SATA: Initializing...\n"); if (config == NULL) { printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); return; } /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); pci_write_config8(dev, 0x09, 0x80); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); /* Setup register 98h */ reg32 = pci_read_config16(dev, 0x98); reg32 |= 1 << 19; /* BWG step 6 */ reg32 |= 1 << 22; /* BWG step 5 */ reg32 &= ~(0x3f << 7); reg32 |= 0x04 << 7; /* BWG step 7 */ reg32 |= 1 << 20; /* BWG step 8 */ reg32 &= ~(0x03 << 5); reg32 |= 1 << 5; /* BWG step 9 */ reg32 |= 1 << 18; /* BWG step 10 */ reg32 |= 1 << 29; /* BWG step 11 */ if (pch_is_lp()) { reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ reg16 = 1 << 5; /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ reg32 = 0x183; reg32 |= (config->sata_port_map ^ 0x3f) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS if (pch_is_lp()) reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); /* Enable DEVSLP */ if (pch_is_lp()) { if (config->sata_devslp_disable) reg32 &= ~(1 << 3); else reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); } else { reg32 &= ~0x00000002; } write32(abar + 0x24, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); /* Native mode capable on both primary and secondary (0xa) * or'ed with enabled (0x50) = 0xf */ pci_write_config8(dev, 0x09, 0x8f); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= config->sata_port_map; pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) pch_iobp_update(SATA_IOBP_SP0G3IR, 0, config->sata_port0_gen3_tx); if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1G3IR, 0, config->sata_port1_gen3_tx); /* Set Gen3 DTLE DATA / EDGE registers if needed */ if (config->sata_port0_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } if (config->sata_port1_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } /* Additional Programming Requirements */ /* Power Optimizer */ /* Step 1 */ if (pch_is_lp()) sir_write(dev, 0x64, 0x883c9003); else sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); /* Step 3: SIR 60h[3] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 3); sir_write(dev, 0x60, reg32); /* Step 4: SIR 60h[0] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 0); sir_write(dev, 0x60, reg32); /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); if (pch_is_lp()) { sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); } reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); }
/* Set bit in Function Disable register to hide this device */ void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ rcba_function_disable(FD, PCH_DISABLE_ADSPD); break; case PCH_DEVFN_XHCI: /* XHCI */ rcba_function_disable(FD, PCH_DISABLE_XHCI); break; case PCH_DEVFN_SDMA: /* DMA */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_I2C0: /* I2C0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_I2C1: /* I2C1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_SPI0: /* SPI0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_SPI1: /* SPI1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_UART0: /* UART0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_UART1: /* UART1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_ME: /* MEI #1 */ rcba_function_disable(FD2, PCH_DISABLE_MEI1); break; case PCH_DEVFN_ME_2: /* MEI #2 */ rcba_function_disable(FD2, PCH_DISABLE_MEI2); break; case PCH_DEVFN_ME_IDER: /* IDE-R */ rcba_function_disable(FD2, PCH_DISABLE_IDER); break; case PCH_DEVFN_ME_KT: /* KT */ rcba_function_disable(FD2, PCH_DISABLE_KT); break; case PCH_DEVFN_SDIO: /* SDIO */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; case PCH_DEVFN_GBE: /* Gigabit Ethernet */ rcba_function_disable(BUC, PCH_DISABLE_GBE); break; case PCH_DEVFN_HDA: /* HD Audio Controller */ rcba_function_disable(FD, PCH_DISABLE_HD_AUDIO); break; case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */ case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */ rcba_function_disable(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); break; case PCH_DEVFN_EHCI: /* EHCI #1 */ rcba_function_disable(FD, PCH_DISABLE_EHCI1); break; case PCH_DEVFN_LPC: /* LPC */ rcba_function_disable(FD, PCH_DISABLE_LPC); break; case PCH_DEVFN_SATA: /* SATA #1 */ rcba_function_disable(FD, PCH_DISABLE_SATA1); break; case PCH_DEVFN_SMBUS: /* SMBUS */ rcba_function_disable(FD, PCH_DISABLE_SMBUS); break; case PCH_DEVFN_SATA2: /* SATA #2 */ rcba_function_disable(FD, PCH_DISABLE_SATA2); break; case PCH_DEVFN_THERMAL: /* Thermal Subsystem */ rcba_function_disable(FD, PCH_DISABLE_THERMAL); break; } }
static void sata_init(struct device *dev) { config_t *config = dev->chip_info; u32 reg32; u8 *abar; u16 reg16; int port; printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0xf; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); /* Setup register 98h */ reg32 = pci_read_config32(dev, 0x98); reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ pci_write_config32(dev, 0x98, reg32); /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ reg16 = 1 << 5; /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ reg32 = 0x183; reg32 |= (config->sata_port_map ^ 0xf) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ if (config->sata_devslp_disable) { reg32 = read32(abar + 0x24); reg32 &= ~(1 << 3); write32(abar + 0x24, reg32); } else { /* Enable DEVSLP */ reg32 = read32(abar + 0x24); reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); write32(abar + 0x24, reg32); for (port = 0; port < 4; port++) { if (!(config->sata_port_map & (1 << port))) continue; reg32 = read32(abar + 0x144 + (0x80 * port)); reg32 |= (1 << 1); /* DEVSLP DSP */ write32(abar + 0x144 + (0x80 * port), reg32); } } /* * Static Power Gating for unused ports */ reg32 = RCBA32(0x3a84); /* Port 3 and 2 disabled */ if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) reg32 |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) reg32 |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = reg32; /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) pch_iobp_update(SATA_IOBP_SP0_SECRT88, ~(SATA_SECRT88_VADJ_MASK << SATA_SECRT88_VADJ_SHIFT), (config->sata_port0_gen3_tx & SATA_SECRT88_VADJ_MASK) << SATA_SECRT88_VADJ_SHIFT); if (config->sata_port1_gen3_tx) pch_iobp_update(SATA_IOBP_SP1_SECRT88, ~(SATA_SECRT88_VADJ_MASK << SATA_SECRT88_VADJ_SHIFT), (config->sata_port1_gen3_tx & SATA_SECRT88_VADJ_MASK) << SATA_SECRT88_VADJ_SHIFT); /* Set Gen3 DTLE DATA / EDGE registers if needed */ if (config->sata_port0_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } if (config->sata_port1_gen3_dtle) { pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_DATA_SHIFT); pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) << SATA_DTLE_EDGE_SHIFT); } /* * Additional Programming Requirements for Power Optimizer */ /* Step 1 */ sir_write(dev, 0x64, 0x883c9003); /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); /* Step 3: SIR 60h[3] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 3); sir_write(dev, 0x60, reg32); /* Step 4: SIR 60h[0] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 0); sir_write(dev, 0x60, reg32); /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16) | (1 << 19); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); reg32 = pci_read_config32(dev, 0x98); reg32 |= 1 << 29; pci_write_config32(dev, 0x98, reg32); /* Register Lock */ reg32 = pci_read_config32(dev, 0x9c); reg32 |= (1 << 31); pci_write_config32(dev, 0x9c, reg32); }