PUBLIC int drv_init_hw (void) { u16_t i, j; u16_t chip_sel_ctrl_reg; /* First, detect the hardware */ if (detect_hw() != OK) { return EIO; } /* PCI command register * enable the SERR# driver, PCI bus mastering and I/O access */ pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS); /* turn everything off */ pci_outl(reg(CHIP_SEL_CTRL), 0x0UL); /* turn off legacy (legacy control is undocumented) */ pci_outl(reg(LEGACY), 0x0UL); pci_outl(reg(LEGACY+4), 0x0UL); /* turn off serial interface */ pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL); /*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/ /* enable the codec */ chip_sel_ctrl_reg = pci_inw(reg(CHIP_SEL_CTRL)); chip_sel_ctrl_reg |= XCTL0 | CDC_EN; pci_outw(reg(CHIP_SEL_CTRL), chip_sel_ctrl_reg); /* initialize the codec */ if (ak4531_init(reg(CODEC_WRITE_ADDRESS), reg(INTERRUPT_STATUS), CWRIP, reg(0)) < 0) { return EINVAL; } /* clear all the memory */ for (i = 0; i < 0x10; ++i) { pci_outb(reg(MEM_PAGE), i); for (j = 0; j < 0x10; j += 4) { pci_outl (reg(MEMORY) + j, 0x0UL); } } /* initialize variables for each sub_device */ for (i = 0; i < drv.NrOfSubDevices; i++) { if(i != MIXER) { aud_conf[i].busy = 0; aud_conf[i].stereo = DEFAULT_STEREO; aud_conf[i].sample_rate = DEFAULT_RATE; aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS; aud_conf[i].sign = DEFAULT_SIGNED; aud_conf[i].fragment_size = sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments; } } return OK; }
int drv_init_hw (void) { u16_t i, j; /* First, detect the hardware */ if (detect_hw() != OK) { return EIO; } /* PCI command register * enable the SERR# driver, PCI bus mastering and I/O access */ pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS); /* turn everything off */ pci_outl(reg(CHIP_SEL_CTRL), 0x0UL); /* turn off legacy (legacy control is undocumented) */ pci_outl(reg(LEGACY), 0x0UL); pci_outl(reg(LEGACY+4), 0x0UL); /* turn off serial interface */ pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL); /*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/ /* clear all the memory */ for (i = 0; i < 0x10; ++i) { pci_outb(reg(MEM_PAGE), i); for (j = 0; j < 0x10; j += 4) { pci_outl (reg(MEMORY) + j, 0x0UL); } } /* Sample Rate Converter initialization */ if (src_init(&dev) != OK) { return EIO; } if (AC97_init(&dev) != OK) { return EIO; } /* initialize variables for each sub_device */ for (i = 0; i < drv.NrOfSubDevices; i++) { if(i != MIXER) { aud_conf[i].busy = 0; aud_conf[i].stereo = DEFAULT_STEREO; aud_conf[i].sample_rate = DEFAULT_RATE; aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS; aud_conf[i].sign = DEFAULT_SIGNED; aud_conf[i].fragment_size = sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments; } } return OK; }
int ddekit_pci_writew (int bus, int slot, int func, int pos, ddekit_uint16_t val) { struct ddekit_pci_dev * dev = ddekit_get_dev_helper(bus, slot, func); if (dev) { pci_attr_w16 (dev->devind, pos, val); DDEBUG_MSG_VERBOSE("bus: %d, slot: %d, func: %d, pos: %x %x", bus,slot,func,pos, val); return 0; } return -1; }
/* * Find a matching device. Return TRUE on success. */ static int e1000_probe(e1000_t * e, int skip) { int r, devind, ioflag; u16_t vid, did, cr; u32_t status; u32_t base, size; char *dname; E1000_DEBUG(3, ("%s: probe()\n", e->name)); /* Initialize communication to the PCI driver. */ pci_init(); /* Attempt to iterate the PCI bus. Start at the beginning. */ if ((r = pci_first_dev(&devind, &vid, &did)) == 0) return FALSE; /* Loop devices on the PCI bus. */ while (skip--) { E1000_DEBUG(3, ("%s: probe() devind %d vid 0x%x did 0x%x\n", e->name, devind, vid, did)); if (!(r = pci_next_dev(&devind, &vid, &did))) return FALSE; } /* We found a matching card. Set card-specific properties. */ e->eeprom_read = eeprom_eerd; switch (did) { case E1000_DEV_ID_ICH10_D_BM_LM: case E1000_DEV_ID_ICH10_R_BM_LF: e->eeprom_read = eeprom_ich; break; case E1000_DEV_ID_82540EM: case E1000_DEV_ID_82545EM: case E1000_DEV_ID_82540EP_LP: e->eeprom_done_bit = (1 << 4); e->eeprom_addr_off = 8; break; default: e->eeprom_done_bit = (1 << 1); e->eeprom_addr_off = 2; break; } /* Inform the user about the new card. */ if (!(dname = pci_dev_name(vid, did))) dname = "Intel Pro/1000 Gigabit Ethernet Card"; E1000_DEBUG(1, ("%s: %s (%04x/%04x) at %s\n", e->name, dname, vid, did, pci_slot_name(devind))); /* Reserve PCI resources found. */ pci_reserve(devind); /* Read PCI configuration. */ e->irq = pci_attr_r8(devind, PCI_ILR); if ((r = pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) != OK) panic("failed to get PCI BAR: %d", r); if (ioflag) panic("PCI BAR is not for memory"); if ((e->regs = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED) panic("failed to map hardware registers from PCI"); /* Enable DMA bus mastering if necessary. */ cr = pci_attr_r16(devind, PCI_CR); if (!(cr & PCI_CR_MAST_EN)) pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN); /* Optionally map flash memory. */ e1000_map_flash(e, devind, did); /* Output debug information. */ status = e1000_reg_read(e, E1000_REG_STATUS); E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n", e->name, e->regs, e->irq)); E1000_DEBUG(3, ("%s: link %s, %s duplex\n", e->name, status & 3 ? "up" : "down", status & 1 ? "full" : "half")); return TRUE; }
/*===========================================================================* * do_int * *===========================================================================*/ static void do_int(struct port *pp) { int devind, vcc_5v, vcc_3v, vcc_Xv, vcc_Yv, socket_5v, socket_3v, socket_Xv, socket_Yv; spin_t spin; u32_t csr_event, csr_present, csr_control; u8_t v8; u16_t v16; #if USE_INTS int r; #endif devind= pp->p_devind; v8= pci_attr_r8(devind, TI_CARD_CTRL); if (v8 & TI_CCR_IFG) { printf("ti1225: got functional interrupt\n"); pci_attr_w8(devind, TI_CARD_CTRL, v8); } if (debug) { printf("Socket event: 0x%x\n", pp->csr_ptr->csr_event); printf("Socket mask: 0x%x\n", pp->csr_ptr->csr_mask); } csr_present= pp->csr_ptr->csr_present; csr_control= pp->csr_ptr->csr_control; if ((csr_present & (CP_CDETECT1|CP_CDETECT2)) != 0) { if (debug) printf("do_int: no card present\n"); return; } if (csr_present & CP_BADVCCREQ) { printf("do_int: Bad Vcc request\n"); /* return; */ } if (csr_present & CP_DATALOST) { /* Do we care? */ if (debug) printf("do_int: Data lost\n"); /* return; */ } if (csr_present & CP_NOTACARD) { printf("do_int: Not a card\n"); return; } if (debug) { if (csr_present & CP_CBCARD) printf("do_int: Cardbus card detected\n"); if (csr_present & CP_16BITCARD) printf("do_int: 16-bit card detected\n"); } if (csr_present & CP_PWRCYCLE) { if (debug) printf("do_int: powered up\n"); return; } vcc_5v= !!(csr_present & CP_5VCARD); vcc_3v= !!(csr_present & CP_3VCARD); vcc_Xv= !!(csr_present & CP_XVCARD); vcc_Yv= !!(csr_present & CP_YVCARD); if (debug) { printf("do_int: card supports:%s%s%s%s\n", vcc_5v ? " 5V" : "", vcc_3v ? " 3V" : "", vcc_Xv ? " X.X V" : "", vcc_Yv ? " Y.Y V" : ""); } socket_5v= !!(csr_present & CP_5VSOCKET); socket_3v= !!(csr_present & CP_3VSOCKET); socket_Xv= !!(csr_present & CP_XVSOCKET); socket_Yv= !!(csr_present & CP_YVSOCKET); if (debug) { printf("do_int: socket supports:%s%s%s%s\n", socket_5v ? " 5V" : "", socket_3v ? " 3V" : "", socket_Xv ? " X.X V" : "", socket_Yv ? " Y.Y V" : ""); } if (vcc_5v && socket_5v) { csr_control= (csr_control & ~CC_VCCCTRL) | CC_VCC_5V; pp->csr_ptr->csr_control= csr_control; if (debug) printf("do_int: applying 5V\n"); } else if (vcc_3v && socket_3v) { csr_control= (csr_control & ~CC_VCCCTRL) | CC_VCC_3V; pp->csr_ptr->csr_control= csr_control; if (debug) printf("do_int: applying 3V\n"); } else if (vcc_Xv && socket_Xv) { csr_control= (csr_control & ~CC_VCCCTRL) | CC_VCC_XV; pp->csr_ptr->csr_control= csr_control; printf("do_int: applying X.X V\n"); } else if (vcc_Yv && socket_Yv) { csr_control= (csr_control & ~CC_VCCCTRL) | CC_VCC_YV; pp->csr_ptr->csr_control= csr_control; printf("do_int: applying Y.Y V\n"); } else { printf("do_int: socket and card are not compatible\n"); return; } csr_event= pp->csr_ptr->csr_event; if (csr_event) { if (debug) printf("clearing socket event\n"); pp->csr_ptr->csr_event= csr_event; if (debug) { printf("Socket event (cleared): 0x%x\n", pp->csr_ptr->csr_event); } } devind= pp->p_devind; v8= pci_attr_r8(devind, TI_CARD_CTRL); if (v8 & TI_CCR_IFG) { printf("ti1225: got functional interrupt\n"); pci_attr_w8(devind, TI_CARD_CTRL, v8); } if (debug) { v8= pci_attr_r8(devind, TI_CARD_CTRL); printf("TI_CARD_CTRL: 0x%02x\n", v8); } spin_init(&spin, 100000); do { csr_present= pp->csr_ptr->csr_present; if (csr_present & CP_PWRCYCLE) break; } while (spin_check(&spin)); if (!(csr_present & CP_PWRCYCLE)) { printf("do_int: not powered up?\n"); return; } /* Reset device */ v16= pci_attr_r16(devind, CBB_BRIDGECTRL); v16 |= CBB_BC_CRST; pci_attr_w16(devind, CBB_BRIDGECTRL, v16); /* Wait one microsecond. Is this correct? What are the specs? */ micro_delay(1); /* Clear CBB_BC_CRST */ v16= pci_attr_r16(devind, CBB_BRIDGECTRL); v16 &= ~CBB_BC_CRST; pci_attr_w16(devind, CBB_BRIDGECTRL, v16); /* Wait one microsecond after clearing the reset line. Is this * correct? What are the specs? */ micro_delay(1); pci_rescan_bus(pp->p_cb_busnr); #if USE_INTS r= sys_irqenable(&pp->p_hook); if (r != OK) panic("unable enable interrupts: %d", r); #endif }
/*===========================================================================* * hw_init * *===========================================================================*/ static void hw_init(struct port *pp, int devind) { u8_t v8; u16_t v16; u32_t v32; #if USE_INTS int r, irq; #endif pp->p_devind= devind; if (debug) printf("hw_init: devind = %d\n", devind); if (debug) { v16= pci_attr_r16(devind, PCI_CR); printf("ti1225: command register 0x%x\n", v16); } v32= pci_attr_r32(devind, TI_CB_BASEADDR); if (debug) printf("ti1225: Cardbus/ExCA base address 0x%x\n", v32); v32 &= PCI_BAR_MEM_MASK; /* Clear low order bits in base */ pp->csr_ptr= (struct csr *) vm_map_phys(SELF, (void *) v32, I386_PAGE_SIZE); if (pp->csr_ptr == MAP_FAILED) panic("hw_init: vm_map_phys failed"); if (debug) { v8= pci_attr_r8(devind, TI_PCI_BUS_NR); printf("ti1225: PCI bus number %d\n", v8); } v8= pci_attr_r8(devind, TI_CB_BUS_NR); pp->p_cb_busnr= v8; if (debug) { printf("ti1225: CardBus bus number %d\n", v8); v8= pci_attr_r8(devind, TI_SO_BUS_NR); printf("ti1225: Subordinate bus number %d\n", v8); } #if USE_INTS irq= pci_attr_r8(devind, PCI_ILR); pp->p_irq= irq; printf("ti1225 using IRQ %d\n", irq); #endif v32= pci_attr_r32(devind, TI_LEGACY_BA); v32 &= ~1; if (debug) { printf("ti1225: PC Card 16-bit legacy-mode base address 0x%x\n", v32); } if (v32 == 0) panic("bad legacy-mode base address: %d", v32); pp->p_exca_port= v32; if (debug) { v32= pci_attr_r32(devind, TI_MF_ROUTE); printf("ti1225: Multifunction routing 0x%08x\n", v32); } #if USE_INTS pp->p_hook = pp->p_irq; r= sys_irqsetpolicy(pp->p_irq, 0, &pp->p_hook); if (r != OK) panic("sys_irqsetpolicy failed: %d", r); #endif /* Clear CBB_BC_INTEXCA */ v16= pci_attr_r16(devind, CBB_BRIDGECTRL); if (debug) printf("ti1225: Bridge control 0x%04x\n", v16); v16 &= ~CBB_BC_INTEXCA; pci_attr_w16(devind, CBB_BRIDGECTRL, v16); if (debug) { v32= pci_attr_r32(devind, TI_SYSCTRL); printf("ti1225: System Control Register 0x%08x\n", v32); v8= pci_attr_r8(devind, TI_CARD_CTRL); printf("ti1225: Card Control 0x%02x\n", v8); v8= pci_attr_r8(devind, TI_DEV_CTRL); printf("ti1225: Device Control 0x%02x\n", v8); } /* Enable socket interrupts */ pp->csr_ptr->csr_mask |= CM_PWRMASK | CM_CDMASK | CM_CSTSMASK; do_int(pp); #if USE_INTS r= sys_irqenable(&pp->p_hook); if (r != OK) panic("unable enable interrupts: %d", r); #endif }