static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
int where, int size, u32 *value)
{
struct pci_pbm_info *pbm = bus_dev->sysdata;
unsigned char bus = bus_dev->number;
u32 *addr;
u16 tmp16;
u8 tmp8;
switch (size) {
case 1:
*value = 0xff;
break;
case 2:
*value = 0xffff;
break;
case 4:
*value = 0xffffffff;
break;
}
addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
if (!addr)
return PCIBIOS_SUCCESSFUL;
if (__sabre_out_of_range(pbm, bus, devfn))
return PCIBIOS_SUCCESSFUL;
switch (size) {
case 1:
pci_config_read8((u8 *) addr, &tmp8);
*value = tmp8;
break;
case 2:
if (where & 0x01) {
printk("pci_read_config_word: misaligned reg [%x]\n",
where);
return PCIBIOS_SUCCESSFUL;
}
pci_config_read16((u16 *) addr, &tmp16);
*value = tmp16;
break;
case 4:
if (where & 0x03) {
printk("pci_read_config_dword: misaligned reg [%x]\n",
where);
return PCIBIOS_SUCCESSFUL;
}
pci_config_read32(addr, value);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static void read_smb_intel(pci_dt_t *smbus_dev)
{
int i, speed;
uint8_t spd_size, spd_type;
uint32_t base, mmio, hostc;
// bool dump = false;
RamSlotInfo_t* slot;
uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);
DBG("SMBus CmdReg: 0x%x\n", cmd);
pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);
mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;
base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);
IOLog("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",
smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);
// Search MAX_RAM_SLOTS slots
// for (i = 0; i < MAX_RAM_SLOTS; i++){
// spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
} // for
void setup_pci_devs(pci_dt_t *pci_dt)
{
char *devicepath;
BOOL do_eth_devprop, do_gfx_devprop, fix_ehci, fix_legoff, fix_uhci, fix_usb, do_enable_hpet;
pci_dt_t *current = pci_dt;
do_eth_devprop = do_gfx_devprop = fix_ehci = fix_legoff = fix_uhci = fix_usb = do_enable_hpet = false;
getBoolForKey("EthernetBuiltIn", &do_eth_devprop, &bootInfo->bootConfig);
getBoolForKey("GraphicsEnabler", &do_gfx_devprop, &bootInfo->bootConfig);
if (getBoolForKey("USBBusFix", &fix_usb, &bootInfo->bootConfig) && fix_usb)
fix_ehci = fix_uhci = true;
else
{
getBoolForKey("EHCIacquire", &fix_ehci, &bootInfo->bootConfig);
getBoolForKey("UHCIreset", &fix_uhci, &bootInfo->bootConfig);
}
getBoolForKey("USBLegacyOff", &fix_legoff, &bootInfo->bootConfig);
getBoolForKey("ForceHPET", &do_enable_hpet, &bootInfo->bootConfig);
while (current)
{
devicepath = get_pci_dev_path(current);
switch (current->class_id)
{
case PCI_CLASS_NETWORK_ETHERNET:
if (do_eth_devprop)
set_eth_builtin(current);
break;
case PCI_CLASS_DISPLAY_VGA:
if (do_gfx_devprop)
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
break;
case PCI_VENDOR_ID_INTEL:
/* message to be removed once support for these cards is added */
verbose("Intel VGA Controller [%04x:%04x] :: %s (currently NOT SUPPORTED)\n",
current->vendor_id, current->device_id, devicepath);
break;
case PCI_VENDOR_ID_NVIDIA:
setup_nvidia_devprop(current);
break;
}
break;
case PCI_CLASS_SERIAL_USB:
switch (pci_config_read8(current->dev.addr, PCI_CLASS_PROG))
{
/* EHCI */
case 0x20:
if (fix_ehci)
ehci_acquire(current);
if (fix_legoff)
legacy_off(current);
break;
/* UHCI */
case 0x00:
if (fix_uhci)
uhci_reset(current);
break;
}
break;
case PCI_CLASS_BRIDGE_ISA:
if (do_enable_hpet)
force_enable_hpet(current);
break;
}
setup_pci_devs(current->children);
current = current->next;
}
}
/* Wrappers for passing PCI config space calls to camkes */
static uint8_t camkes_pci_read8(void *cookie, vmm_pci_address_t addr, unsigned int offset) {
return pci_config_read8(addr.bus, addr.dev, addr.fun, offset);
}
