static void vortex86mx_sb_set_resources(device_t dev) { //struct resource *resource; //resource = find_resource(dev,1); //resource->flags |= IORESOURCE_STORED; pci_dev_set_resources(dev); }
static void vx800_set_resources(device_t dev) { struct resource *resource; resource = find_resource(dev, 1); resource->flags |= IORESOURCE_STORED; pci_dev_set_resources(dev); }
static void pch_lpc_set_resources(struct device *dev) { pci_dev_set_resources(dev); /* Now open up windows to devices which have declared resources. */ pch_lpc_set_child_resources(dev); }
static void sb800_sm_set_resources(struct device *dev) { struct resource *res; u8 byte; pci_dev_set_resources(dev); /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte); res = find_resource(dev, 0x74); printk(BIOS_INFO, "sb800_sm_set_resources, res->base=0x%llx\n", res->base); //pci_write_config32(dev, 0x74, res->base | 1 << 3); pm_iowrite(0x34, res->base | 0x7); pm_iowrite(0x35, (res->base >> 8) & 0xFF); pm_iowrite(0x36, (res->base >> 16) & 0xFF); pm_iowrite(0x37, (res->base >> 24) & 0xFF); #if 0 /* TODO:hpet */ res = find_resource(dev, 0x14); pci_write_config32(dev, 0x14, res->base); #endif //res = find_resource(dev, 0x90); //pci_write_config32(dev, 0x90, res->base | 1); }
static void oxford_oxpcie_set_resources(struct device *dev) { pci_dev_set_resources(dev); /* Re-initialize OXPCIe base address after set_resources */ u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); oxford_remap(mmio_base & ~0xf); }
static void pcixx12_set_resources(device_t dev) { printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); pci_dev_set_resources(dev); printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev)); }
static void sis761_set_resources(device_t dev) { printk(BIOS_DEBUG, "sis761_set_resources ------->\n"); /* Set the generic PCI resources */ pci_dev_set_resources(dev); printk(BIOS_DEBUG, "sis761_set_resources <-------\n"); }
static void pci7420_cardbus_set_resources(struct device *dev) { printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); pci_dev_set_resources(dev); printk(BIOS_DEBUG, "%s done set resources\n",dev_path(dev)); }
static void set_resources(device_t dev) { pci_dev_set_resources(dev); /* Close all previously opened windows and allocate from scratch. */ lpc_close_pmio_windows(); /* Now open up windows to devices which have declared resources. */ set_child_resources(dev); }
static void hudson_lpc_set_resources(struct device *dev) { struct resource *res; /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, 2); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); pci_dev_set_resources(dev); }
static void sb700_lpc_set_resources(struct device *dev) { struct resource *res; pci_dev_set_resources(dev); /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, 0xA0); pci_write_config32(dev, 0xA0, res->base | 1 << 1); }
void lpc_set_resources(struct device *dev) { struct resource *res; pci_dev_set_resources(dev); /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); }
static void hudson_lpc_set_resources(struct device *dev) { struct resource *res; /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS_REGISTER); res->base |= PCI_COMMAND_MEMORY; pci_dev_set_resources(dev); }
void lpc_set_resources(struct device *dev) { struct resource *res; printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); pci_dev_set_resources(dev); /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); }
static void iommu_set_resources(device_t dev) { struct resource *res; pci_dev_set_resources(dev); res = find_resource(dev, 0x44); /* Remember this resource has been stored */ res->flags |= IORESOURCE_STORED; /* For now, do only 32-bit space allocation */ pci_write_config32(dev, 0x48, 0x0); pci_write_config32(dev, 0x44, res->base | (1 << 0)); }
static void serialio_set_resources(struct device *dev) { pci_dev_set_resources(dev); #if CONFIG_INTEL_PCH_UART_CONSOLE /* Update UART base address if used for debug */ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) uartmem_setbaseaddr(res->base); } #endif }
static void lpe_set_resources(device_t dev) { struct resource *res; pci_dev_set_resources(dev); res = find_resource(dev, FIRMWARE_REG_BASE); if (res == NULL) { printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); return; } pci_write_config32(dev, FIRMWARE_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size); }
void lpc_set_resources(struct device *dev) { struct resource *res; printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, 2); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); pci_dev_set_resources(dev); printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); }
static void rl5c476_set_resources(device_t dev) { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; } } pci_dev_set_resources(dev); }
static void set_resources(device_t dev) { struct resource *res; pci_dev_set_resources(dev); res = find_resource(dev, PCI_BASE_ADDRESS_0); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_MEMORY; res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, " SRAM BAR 0"); res = find_resource(dev, PCI_BASE_ADDRESS_2); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_MEMORY; res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, " SRAM BAR 1"); }
static void usb_set_resources(struct device *dev) { struct resource *res; u32 base; u32 old_debug; old_debug = get_ehci_debug(); set_ehci_debug(0); pci_dev_set_resources(dev); res = find_resource(dev, 0x10); set_ehci_debug(old_debug); if (!res) return; base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); }
static void mmconfig_set_resources(device_t dev) { struct resource *resource; u8 reg; resource = find_resource(dev, K8T890_MMCONFIG_MBAR); if (resource) { report_resource_stored(dev, resource, "<mmconfig>"); /* Remember this resource has been stored. */ resource->flags |= IORESOURCE_STORED; pci_write_config8(dev, K8T890_MMCONFIG_MBAR, (resource->base >> 28)); reg = pci_read_config8(dev, 0x60); reg |= 0x3; /* Enable MMCONFIG decoding. */ pci_write_config8(dev, 0x60, reg); } pci_dev_set_resources(dev); }
static void sb600_sm_set_resources(struct device *dev) { struct resource *res; u8 byte; pci_dev_set_resources(dev); /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte); res = find_resource(dev, 0x74); pci_write_config32(dev, 0x74, res->base | 1 << 3); res = find_resource(dev, 0x14); pci_write_config32(dev, 0x14, res->base); res = find_resource(dev, 0x10); pci_write_config32(dev, 0x10, res->base | 1); }
static void usb_ehci_set_resources(struct device *dev) { #if CONFIG_USBDEBUG struct resource *res; u32 base; u32 usb_debug; usb_debug = get_ehci_debug(); set_ehci_debug(0); #endif pci_dev_set_resources(dev); #if CONFIG_USBDEBUG res = find_resource(dev, 0x10); set_ehci_debug(usb_debug); if (!res) return; base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); #endif }
static void sb700_sm_set_resources(struct device *dev) { struct resource *res; u8 byte; pci_dev_set_resources(dev); res = find_resource(dev, 0x74); pci_write_config32(dev, 0x74, res->base | 1 << 3); /* TODO: test hpet */ #if 0 //rrg-2.0.3 shows BAR1 not used /* Make SMBUS BAR1(HPET base at offset 14h) visible */ byte = pci_read_config8(dev, 0x43); byte &= ~(1 << 3); pci_write_config8(dev, 0x43, byte); #endif res = find_resource(dev, 0xB4); /* Program HPET BAR Address */ pci_write_config32(dev, 0xB4, res->base); /* Enable decoding of HPET MMIO, enable HPET MSI */ byte = pci_read_config8(dev, 0x43); //byte |= (1 << 3); // Make SMBus Bar1 invisible //byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); byte |= (1 << 4); pci_write_config8(dev, 0x43, byte); /* Enable HPET irq */ byte = pci_read_config8(dev, 0x65); byte |= (1 << 2); pci_write_config8(dev, 0x65, byte); /* TODO: End of test hpet */ res = find_resource(dev, PRIMARY_SMBUS_RESOURCE_NUMBER); pci_write_config32(dev, PRIMARY_SMBUS_RESOURCE_NUMBER, res->base | 1); res = find_resource(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER); pci_write_config32(dev, AUXILIARY_SMBUS_RESOURCE_NUMBER, res->base | 1); }
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void rd890_set_resources(struct device *dev) { pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_dev_set_resources(dev); }