static void sb900_enable_rom(void)
{
u32 word;
u32 dword;
device_t dev;
dev = PCI_DEV(0, 0x14, 0x03);
/* SB900 LPC Bridge 0:20:3:44h.
* BIT6: Port Enable for serial port 0x3f8-0x3ff
* BIT29: Port Enable for KBC port 0x60 and 0x64
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
*/
dword = pci_io_read_config32(dev, 0x44);
//dword |= (1<<6) | (1<<29) | (1<<30) ;
/*Turn on all of LPC IO Port decode enable */
dword = 0xffffffff;
pci_io_write_config32(dev, 0x44, dword);
/* SB900 LPC Bridge 0:20:3:48h.
* BIT0: Port Enable for SuperIO 0x2E-0x2F
* BIT1: Port Enable for SuperIO 0x4E-0x4F
* BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
* BIT6: Port Enable for RTC IO 0x70-0x73
* BIT21: Port Enable for Port 0x80
*/
dword = pci_io_read_config32(dev, 0x48);
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0;
pci_io_write_config16(dev, 0x6c, word);
}
void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
{
device_t dev = NB_DEV_ROOT;
/* Set PCI Express BAR */
pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
/*
* Clear TSEG register - TSEG register comes out of reset with a
* non-zero default value. Clear this register to ensure that there are
* no surprises in CBMEM handling.
*/
pci_write_config32(dev, TSEG, 0);
dev = P2SB_DEV;
/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Decode the ACPI I/O port range for early firmware verification.*/
dev = PMC_DEV;
pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MASTER);
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp);
}
void gm45_early_init(void)
{
const device_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup PCIEXBAR. */
pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO,
/* 64MB, enable */
DEFAULT_PCIEXBAR | (2 << 1) | 1);
/* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */
pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
}
static void setup_mmconfig(void)
{
uint32_t reg;
/* Set up the MMCONF range. The register lives in the BUNIT. The
* IO variant of the config access needs to be used initially to
* properly configure as the IOSF access registers live in PCI
* config space. */
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
}
static void bootblock_northbridge_init(void)
{
uint32_t reg32;
/* Disable LaGrande Technology (LT) */
reg32 = TPM32(0);
reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg32);
}
static void bootblock_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
reg = 0;
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
}
void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo)
{
device_t dev = NB_DEV_ROOT;
/* Set PCI Express BAR */
pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
dev = P2SB_DEV;
/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo);
}
