static void i82801ix_pcie_init(const config_t *const info)
{
device_t pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
u32 reg32;
/* PCIe - BIOS must program... */
for (i = 0; i < 6; ++i) {
pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i));
if (!pciePort[i]) {
printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
die(" is not listed in devicetree.\n");
}
#if CONFIG_MMCONF_SUPPORT
reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
pci_mmio_write_config8(pciePort[i], 0x324, 0x40);
#else
#error "MMIO needed for ICH9 PCIe"
#endif
}
if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) {
for (i = 0; i < 6; ++i) {
if (pciePort[i]->enabled) {
reg32 = pci_read_config32(pciePort[i], 0xe8);
reg32 |= 1;
pci_write_config32(pciePort[i], 0xe8, reg32);
}
}
}
for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) {
/* Only for the top disabled ports. */
#if CONFIG_MMCONF_SUPPORT
reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
reg32 |= 0x3 << 16;
pci_mmio_write_config32(pciePort[i], 0x300, reg32);
#else
#error "MMIO needed for ICH9 PCIe"
#endif
}
/* Set slot implemented, slot number and slot power limits. */
for (i = 0; i < 6; ++i) {
const device_t dev = pciePort[i];
u32 xcap = pci_read_config32(dev, D28Fx_XCAP);
if (info->pcie_slot_implemented & (1 << i))
xcap |= PCI_EXP_FLAGS_SLOT;
else
xcap &= ~PCI_EXP_FLAGS_SLOT;
pci_write_config32(dev, D28Fx_XCAP, xcap);
if (info->pcie_slot_implemented & (1 << i)) {
u32 slcap = pci_read_config32(dev, D28Fx_SLCAP);
slcap &= ~(0x1fff << 19);
slcap |= (slot_number++ << 19);
slcap &= ~(0x0003 << 16);
slcap |= (info->pcie_power_limits[i].scale << 16);
slcap &= ~(0x00ff << 7);
slcap |= (info->pcie_power_limits[i].value << 7);
pci_write_config32(dev, D28Fx_SLCAP, slcap);
}
}
/* Lock R/WO ASPM support bits. */
for (i = 0; i < 6; ++i) {
reg32 = pci_read_config32(pciePort[i], 0x4c);
pci_write_config32(pciePort[i], 0x4c, reg32);
}
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u32 reg32;
#if CONFIG_MMCONF_SUPPORT
// ESD
reg32 = pci_mmio_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x134, reg32);
// Link1 description
reg32 = pci_mmio_read_config32(dev, 0x140);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_mmio_write_config32(dev, 0x114, reg32);
// VCi traffic class
reg8 = pci_mmio_read_config8(dev, 0x44);
reg8 |= (7 << 0); // TC7
pci_mmio_write_config8(dev, 0x44, reg8);
// VCi Resource Control
reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 |= (1 << 31);
reg32 |= (1 << 24); // VCi ID
reg32 |= (0x80 << 0); // VCi map
pci_mmio_write_config32(dev, 0x120, reg32);
#else
#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
#endif
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
// TODO Actually check if we're AC97 or HDA instead of hardcoding this
// here, in devicetree.cb and/or romstage.c.
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); // Clear Clock Detect Bit
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); // Enable clock detection
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
#if 0
/* Set routing pin */
pci_write_config32(dev, 0xf8, 0x0);
pci_write_config8(dev, 0xfc, 0xAA);
/* Set INTA */
pci_write_config8(dev, 0x63, 0x0);
/* Enable azalia, disable ac97 */
// pm_iowrite(0x59, 0xB);
#endif
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
}
