/*
* Machine independent support for PCI serial console support.
*
* Scan the PCI bus for something which resembles a 16550
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: puccn.c,v 1.9 2007/01/13 18:59:31 cube Exp $");
#include "opt_kgdb.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <sys/termios.h>
#include <dev/ic/comreg.h>
#include <dev/ic/comvar.h>
#include <dev/cons.h>
#include <dev/pci/pucvar.h>
#include <dev/pci/puccn.h>
#ifndef CONSPEED
#define CONSPEED TTYDEF_SPEED
#endif
#ifndef CONMODE
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE|CSTOPB|PARENB))|CS8) /* 8N1 */
#endif
#ifdef i386 /* Handle i386 directly */
int
cpu_comcnprobe(struct consdev *cn, struct pci_attach_args *pa)
{
pci_mode_detect();
pa->pa_iot = X86_BUS_SPACE_IO;
pa->pa_pc = 0;
pa->pa_tag = pci_make_tag(0, 0, 31, 0);
return 0;
}
/*
* 1st pass on BIOS's Intel MP specification table.
*
* initializes:
* mp_ncpus = 1
*
* determines:
* cpu_apic_address (common to all CPUs)
* ioapic_address[N]
* mp_naps
* mp_nbusses
* mp_napics
* nintrs
*/
void
mpbios_scan(struct device *self)
{
const u_int8_t *position, *end;
int count;
int type;
int intr_cnt;
paddr_t lapic_base;
printf(": Intel MP Specification 1.%d\n", mp_fps->spec_rev);
/*
* looks like we've got a MP system. start setting up
* infrastructure..
* XXX is this the right place??
*/
lapic_base = LAPIC_BASE;
if (mp_cth != NULL)
lapic_base = (paddr_t)mp_cth->apic_address;
lapic_boot_init(lapic_base);
/* check for use of 'default' configuration */
if (mp_fps->mpfb1 != 0) {
struct mpbios_proc pe;
printf("%s: MP default configuration %d\n",
self->dv_xname, mp_fps->mpfb1);
/* use default addresses */
pe.apic_id = cpu_number();
pe.cpu_flags = PROCENTRY_FLAG_EN|PROCENTRY_FLAG_BP;
pe.cpu_signature = cpu_info_primary.ci_signature;
pe.feature_flags = cpu_info_primary.ci_feature_flags;
mpbios_cpu((u_int8_t *)&pe, self);
pe.apic_id = 1 - cpu_number();
pe.cpu_flags = PROCENTRY_FLAG_EN;
mpbios_cpu((u_int8_t *)&pe, self);
mpbios_ioapic((u_int8_t *)&default_ioapic, self);
/* XXX */
printf("%s: WARNING: interrupts not configured\n",
self->dv_xname);
panic("lazy bum");
return;
} else {
/*
* should not happen; mp_probe returns 0 in this case,
* but..
*/
if (mp_cth == NULL)
panic("mpbios_scan: no config (can't happen?)");
/*
* Walk the table once, counting items
*/
for (count = mp_cth->entry_count,
position = (const u_int8_t *)mp_cth + sizeof(*mp_cth),
end = position + mp_cth->base_len;
count-- && position < end;
position += mp_conf[type].length) {
type = *position;
if (type >= MPS_MCT_NTYPES) {
printf("%s: unknown entry type %x"
" in MP config table\n",
self->dv_xname, type);
end = position;
break;
}
mp_conf[type].count++;
}
/*
* Walk the table twice, counting int and bus entries
*/
for (count = mp_cth->entry_count,
intr_cnt = 15, /* presume all isa irqs missing */
position = (const u_int8_t *)mp_cth + sizeof(*mp_cth);
count-- && position < end;
position += mp_conf[type].length) {
type = *position;
if (type == MPS_MCT_BUS) {
const struct mpbios_bus *bp =
(const struct mpbios_bus *)position;
if (bp->bus_id >= mp_nbusses)
mp_nbusses = bp->bus_id + 1;
}
/*
* Count actual interrupt instances.
* dst_apic_id of MPS_ALL_APICS means "wired to all
* apics of this type".
*/
if ((type == MPS_MCT_IOINT) ||
(type == MPS_MCT_LINT)) {
const struct mpbios_int *ie =
(const struct mpbios_int *)position;
if (ie->dst_apic_id != MPS_ALL_APICS)
intr_cnt++;
else if (type == MPS_MCT_IOINT)
intr_cnt +=
mp_conf[MPS_MCT_IOAPIC].count;
else
intr_cnt += mp_conf[MPS_MCT_CPU].count;
}
}
mp_busses = mallocarray(mp_nbusses, sizeof(struct mp_bus),
M_DEVBUF, M_NOWAIT|M_ZERO);
mp_intrs = mallocarray(intr_cnt, sizeof(struct mp_intr_map),
M_DEVBUF, M_NOWAIT);
/* re-walk the table, recording info of interest */
position = (const u_int8_t *)mp_cth + sizeof(*mp_cth);
count = mp_cth->entry_count;
mp_nintrs = 0;
while ((count--) && (position < end)) {
switch (type = *(u_char *)position) {
case MPS_MCT_CPU:
mpbios_cpu(position, self);
break;
case MPS_MCT_BUS:
mpbios_bus(position, self);
break;
case MPS_MCT_IOAPIC:
mpbios_ioapic(position, self);
break;
case MPS_MCT_IOINT:
case MPS_MCT_LINT:
if (mpbios_int(position,
&mp_intrs[mp_nintrs]) == 0)
mp_nintrs++;
break;
default:
printf("%s: unknown entry type %x "
"in MP config table\n",
self->dv_xname, type);
/* NOTREACHED */
return;
}
position += mp_conf[type].length;
}
if (mp_verbose && mp_cth->ext_len)
printf("%s: MP WARNING: %d "
"bytes of extended entries not examined\n",
self->dv_xname, mp_cth->ext_len);
}
/* Clean up. */
mp_fps = NULL;
mpbios_unmap(&mp_fp_map);
if (mp_cth != NULL) {
mp_cth = NULL;
mpbios_unmap(&mp_cfg_table_map);
}
#if NPCI > 0
if (pci_mode_detect() != 0)
mpbios_intr_fixup();
#endif
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
union mainbus_attach_args mba;
#if defined(DOM0OPS) && defined(XEN3)
int numcpus = 0;
#ifdef MPBIOS
int mpbios_present = 0;
#endif
#if NACPI > 0 || defined(MPBIOS)
int numioapics = 0;
#endif
#endif /* defined(DOM0OPS) && defined(XEN3) */
aprint_naive("\n");
aprint_normal("\n");
#ifndef XEN3
memset(&mba.mba_caa, 0, sizeof(mba.mba_caa));
mba.mba_caa.cpu_number = 0;
mba.mba_caa.cpu_role = CPU_ROLE_SP;
mba.mba_caa.cpu_func = 0;
config_found_ia(self, "cpubus", &mba.mba_caa, mainbus_print);
#else /* XEN3 */
#ifdef DOM0OPS
if (xendomain_is_dom0()) {
#ifdef MPBIOS
mpbios_present = mpbios_probe(self);
#endif
#if NPCI > 0
/* ACPI needs to be able to access PCI configuration space. */
pci_mode = pci_mode_detect();
#ifdef PCI_BUS_FIXUP
pci_maxbus = pci_bus_fixup(NULL, 0);
aprint_debug_dev(self, "PCI bus max, after pci_bus_fixup: %i\n",
pci_maxbus);
#ifdef PCI_ADDR_FIXUP
pciaddr.extent_port = NULL;
pciaddr.extent_mem = NULL;
pci_addr_fixup(NULL, pci_maxbus);
#endif /* PCI_ADDR_FIXUP */
#endif /* PCI_BUS_FIXUP */
#if NACPI > 0
acpi_present = acpi_probe();
if (acpi_present)
mpacpi_active = mpacpi_scan_apics(self,
&numcpus, &numioapics);
if (!mpacpi_active)
#endif
{
#ifdef MPBIOS
if (mpbios_present)
mpbios_scan(self, &numcpus, &numioapics);
else
#endif
if (numcpus == 0) {
memset(&mba.mba_caa, 0, sizeof(mba.mba_caa));
mba.mba_caa.cpu_number = 0;
mba.mba_caa.cpu_role = CPU_ROLE_SP;
mba.mba_caa.cpu_func = 0;
config_found_ia(self, "cpubus",
&mba.mba_caa, mainbus_print);
}
}
#if NIOAPIC > 0
ioapic_enable();
#endif
#endif /* NPCI */
}
#endif /* DOM0OPS */
#endif /* XEN3 */
#if NIPMI > 0
memset(&mba.mba_ipmi, 0, sizeof(mba.mba_ipmi));
mba.mba_ipmi.iaa_iot = X86_BUS_SPACE_IO;
mba.mba_ipmi.iaa_memt = X86_BUS_SPACE_MEM;
if (ipmi_probe(&mba.mba_ipmi))
config_found_ia(self, "ipmibus", &mba.mba_ipmi, 0);
#endif
#if NHYPERVISOR > 0
mba.mba_haa.haa_busname = "hypervisor";
config_found_ia(self, "hypervisorbus", &mba.mba_haa, mainbus_print);
#endif
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(struct device *parent, struct device *self, void *aux)
{
union mainbus_attach_args mba;
extern void (*setperf_setup)(struct cpu_info *);
extern void (*cpusensors_setup)(struct cpu_info *);
printf("\n");
#if NBIOS > 0
{
mba.mba_bios.ba_name = "bios";
mba.mba_bios.ba_iot = I386_BUS_SPACE_IO;
mba.mba_bios.ba_memt = I386_BUS_SPACE_MEM;
config_found(self, &mba.mba_bios, mainbus_print);
}
#endif
#if NIPMI > 0
{
memset(&mba.mba_iaa, 0, sizeof(mba.mba_iaa));
mba.mba_iaa.iaa_name = "ipmi";
mba.mba_iaa.iaa_iot = I386_BUS_SPACE_IO;
mba.mba_iaa.iaa_memt = I386_BUS_SPACE_MEM;
if (ipmi_probe(&mba.mba_iaa))
config_found(self, &mba.mba_iaa, mainbus_print);
}
#endif
#if NVMT > 0
if (vmt_probe()) {
mba.mba_busname = "vmware";
config_found(self, &mba.mba_busname, mainbus_print);
}
#endif
#if NMPBIOS > 0
if (mpbios_probe(self))
mpbios_scan(self);
#endif
if ((cpu_info_primary.ci_flags & CPUF_PRESENT) == 0) {
struct cpu_attach_args caa;
memset(&caa, 0, sizeof(caa));
caa.caa_name = "cpu";
caa.cpu_number = 0;
caa.cpu_role = CPU_ROLE_SP;
caa.cpu_func = 0;
caa.cpu_signature = cpu_id;
caa.feature_flags = cpu_feature;
config_found(self, &caa, mainbus_print);
}
#if NAMDMSR > 0
if (amdmsr_probe()) {
mba.mba_busname = "amdmsr";
config_found(self, &mba.mba_busname, mainbus_print);
}
#endif
#if NACPI > 0
if (!acpi_hasprocfvs)
#endif
{
if (setperf_setup != NULL)
setperf_setup(&cpu_info_primary);
}
#ifdef MULTIPROCESSOR
mp_setperf_init();
#endif
if (cpusensors_setup != NULL)
cpusensors_setup(&cpu_info_primary);
#if NVESABIOS > 0
if (vbeprobe()) {
mba.mba_busname = "vesabios";
config_found(self, &mba.mba_busname, NULL);
}
#endif
#if NESM > 0
{
memset(&mba.mba_eaa, 0, sizeof(mba.mba_eaa));
mba.mba_eaa.eaa_name = "esm";
mba.mba_eaa.eaa_iot = I386_BUS_SPACE_IO;
mba.mba_eaa.eaa_memt = I386_BUS_SPACE_MEM;
if (esm_probe(&mba.mba_eaa))
config_found(self, &mba.mba_eaa, mainbus_print);
}
#endif
/*
* XXX Note also that the presence of a PCI bus should
* XXX _always_ be checked, and if present the bus should be
* XXX 'found'. However, because of the structure of the code,
* XXX that's not currently possible.
*/
#if NPCI > 0
if (pci_mode_detect() != 0) {
mba.mba_pba.pba_busname = "pci";
mba.mba_pba.pba_iot = I386_BUS_SPACE_IO;
mba.mba_pba.pba_memt = I386_BUS_SPACE_MEM;
mba.mba_pba.pba_dmat = &pci_bus_dma_tag;
mba.mba_pba.pba_domain = pci_ndomains++;
mba.mba_pba.pba_bus = 0;
mba.mba_pba.pba_bridgetag = NULL;
config_found(self, &mba.mba_pba, mainbus_print);
}
#endif
if (!bcmp(ISA_HOLE_VADDR(EISA_ID_PADDR), EISA_ID, EISA_ID_LEN)) {
mba.mba_eba.eba_busname = "eisa";
mba.mba_eba.eba_iot = I386_BUS_SPACE_IO;
mba.mba_eba.eba_memt = I386_BUS_SPACE_MEM;
#if NEISA > 0
mba.mba_eba.eba_dmat = &eisa_bus_dma_tag;
#endif
config_found(self, &mba.mba_eba, mainbus_print);
}
if (isa_has_been_seen == 0) {
mba.mba_iba.iba_busname = "isa";
mba.mba_iba.iba_iot = I386_BUS_SPACE_IO;
mba.mba_iba.iba_memt = I386_BUS_SPACE_MEM;
#if NISADMA > 0
mba.mba_iba.iba_dmat = &isa_bus_dma_tag;
#endif
config_found(self, &mba.mba_iba, mainbus_print);
}
}
/*
* Attach the mainbus.
*/
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
#if NPCI > 0
union mainbus_attach_args mba;
#endif
#if NACPI > 0
int acpi_present = 0;
#endif
#ifdef MPBIOS
int mpbios_present = 0;
#endif
int mpacpi_active = 0;
int numcpus = 0;
#if NACPI > 0 || defined(MPBIOS)
int numioapics = 0;
#endif
#if defined(PCI_BUS_FIXUP)
int pci_maxbus = 0;
#endif
aprint_naive("\n");
aprint_normal("\n");
#ifdef MPBIOS
mpbios_present = mpbios_probe(self);
#endif
#if NPCI > 0
pci_mode = pci_mode_detect();
#if defined(PCI_BUS_FIXUP)
if (pci_mode != 0) {
pci_maxbus = pci_bus_fixup(NULL, 0);
aprint_debug("PCI bus max, after pci_bus_fixup: %i\n",
pci_maxbus);
#if defined(PCI_ADDR_FIXUP)
pciaddr.extent_port = NULL;
pciaddr.extent_mem = NULL;
pci_addr_fixup(NULL, pci_maxbus);
#endif
}
#endif
#endif
#if NACPI > 0
if ((boothowto & RB_MD2) == 0 && acpi_check(self, "acpibus"))
acpi_present = acpi_probe();
/*
* First, see if the MADT contains CPUs, and possibly I/O APICs.
* Building the interrupt routing structures can only
* be done later (via a callback).
*/
if (acpi_present)
mpacpi_active = mpacpi_scan_apics(self, &numcpus, &numioapics);
#endif
if (!mpacpi_active) {
#ifdef MPBIOS
if (mpbios_present)
mpbios_scan(self, &numcpus, &numioapics);
else
#endif
if (numcpus == 0) {
struct cpu_attach_args caa;
memset(&caa, 0, sizeof(caa));
caa.cpu_number = 0;
caa.cpu_role = CPU_ROLE_SP;
caa.cpu_func = 0;
config_found_ia(self, "cpubus", &caa, mainbus_print);
}
}
#if NISADMA > 0 && NACPI > 0
/*
* ACPI needs ISA DMA initialized before they start probing.
*/
isa_dmainit(&x86_isa_chipset, X86_BUS_SPACE_IO, &isa_bus_dma_tag,
self);
#endif
#if NACPI > 0
if (acpi_present) {
mba.mba_acpi.aa_iot = X86_BUS_SPACE_IO;
mba.mba_acpi.aa_memt = X86_BUS_SPACE_MEM;
mba.mba_acpi.aa_pc = NULL;
mba.mba_acpi.aa_pciflags =
PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
PCI_FLAGS_MWI_OKAY;
mba.mba_acpi.aa_ic = &x86_isa_chipset;
config_found_ia(self, "acpibus", &mba.mba_acpi, 0);
}
#endif
#if NIPMI > 0
memset(&mba.mba_ipmi, 0, sizeof(mba.mba_ipmi));
mba.mba_ipmi.iaa_iot = X86_BUS_SPACE_IO;
mba.mba_ipmi.iaa_memt = X86_BUS_SPACE_MEM;
if (ipmi_probe(&mba.mba_ipmi))
config_found_ia(self, "ipmibus", &mba.mba_ipmi, 0);
#endif
#if NPCI > 0
if (pci_mode != 0) {
mba.mba_pba.pba_iot = X86_BUS_SPACE_IO;
mba.mba_pba.pba_memt = X86_BUS_SPACE_MEM;
mba.mba_pba.pba_dmat = &pci_bus_dma_tag;
mba.mba_pba.pba_dmat64 = &pci_bus_dma64_tag;
mba.mba_pba.pba_pc = NULL;
mba.mba_pba.pba_flags = pci_bus_flags();
mba.mba_pba.pba_bus = 0;
mba.mba_pba.pba_bridgetag = NULL;
#if NACPI > 0 && defined(ACPI_SCANPCI)
if (mpacpi_active)
mpacpi_scan_pci(self, &mba.mba_pba, pcibusprint);
else
#endif
#if defined(MPBIOS) && defined(MPBIOS_SCANPCI)
if (mpbios_scanned != 0)
mpbios_scan_pci(self, &mba.mba_pba, pcibusprint);
else
#endif
config_found_ia(self, "pcibus", &mba.mba_pba, pcibusprint);
#if NACPI > 0
if (mp_verbose)
acpi_pci_link_state();
#endif
}
#endif
#if NISA > 0
if (isa_has_been_seen == 0)
config_found_ia(self, "isabus", &mba_iba, isabusprint);
#endif
if (!pmf_device_register(self, NULL, NULL))
aprint_error_dev(self, "couldn't establish power handler\n");
}
