void *
kse_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned i, val, fdx;
uint8_t *en;
l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x10));
en = data;
i = CSR_READ_2(l, MARL);
en[0] = i;
en[1] = i >> 8;
i = CSR_READ_2(l, MARM);
en[2] = i;
en[3] = i >> 8;
i = CSR_READ_2(l, MARH);
en[4] = i;
en[5] = i >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
CSR_WRITE_2(l, CIDR, 1);
mii_dealan(l, 5);
val = pcicfgread(tag, PCI_ID_REG);
if (PCI_PRODUCT(val) == 0x8841) {
val = CSR_READ_4(l, P1SR);
fdx = !!(val & (1U << 9));
printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
}
txd = &l->txd;
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
rxd[1].xd3 = htole32(VTOPHYS(&rxd[0]));
l->rx = 0;
CSR_WRITE_4(l, TDLB, VTOPHYS(txd));
CSR_WRITE_4(l, RDLB, VTOPHYS(rxd));
CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */
CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */
CSR_WRITE_4(l, MDRSC, 01); /* start receiving */
return l;
}
static void
iteidefix(struct dkdev_ata *l)
{
unsigned v;
/* set PCI mode and 66Mhz reference clock, disable IT8212 RAID */
v = pcicfgread(l->tag, 0x50);
pcicfgwrite(l->tag, 0x50, v & ~0x83);
/* i/o configuration, enable channels, cables, IORDY */
v = pcicfgread(l->tag, 0x40);
pcicfgwrite(l->tag, 0x40, (v & ~0xffffff) | 0x36a0f3);
}
static void
cmdidefix(struct dkdev_ata *l)
{
unsigned v;
v = pcicfgread(l->tag, 0x80);
pcicfgwrite(l->tag, 0x80, (v & ~0xff) | 0x01);
v = pcicfgread(l->tag, 0x84);
pcicfgwrite(l->tag, 0x84, (v & ~0xff) | 0x01);
v = pcicfgread(l->tag, 0xa4);
pcicfgwrite(l->tag, 0xa4, (v & ~0xffff) | 0x328a);
v = pcicfgread(l->tag, 0xb4);
pcicfgwrite(l->tag, 0xb4, (v & ~0xffff) | 0x328a);
}
int
pciide_match(unsigned tag, void *data)
{
unsigned v;
v = pcicfgread(tag, PCI_ID_REG);
switch (v) {
case PCI_DEVICE(0x1095, 0x0680): /* SiI 0680 IDE */
myops = &cmdideops;
return 1;
case PCI_DEVICE(0x1106, 0x0571): /* VIA 82C586A/B/686A/B IDE */
case PCI_DEVICE(0x1106, 0x1571): /* VIA 82C586 IDE */
case PCI_DEVICE(0x1106, 0x3164): /* VIA VT6410 RAID IDE */
myops = &apoideops;
return 1;
case PCI_DEVICE(0x1283, 0x8211): /* ITE 8211 IDE */
myops = &iteideops;
return 1;
case PCI_DEVICE(0x10ad, 0x0105): /* Symphony Labs 82C105 IDE */
case PCI_DEVICE(0x10b8, 0x5229): /* ALi IDE */
case PCI_DEVICE(0x1191, 0x0008): /* ACARD ATP865 */
case PCI_DEVICE(0x1191, 0x0009): /* ACARD ATP865A */
myops = &defaultops;
return 1;
}
return 0;
}
static void
apoidefix(struct dkdev_ata *l)
{
unsigned v;
/* enable primary and secondary channel */
v = pcicfgread(l->tag, 0x40) & ~0x03;
pcicfgwrite(l->tag, 0x40, v | 0x03);
}
int
sme_match(unsigned tag, void *data)
{
unsigned v;
v = pcicfgread(tag, PCI_ID_REG);
switch (v) {
case PCI_DEVICE(0x1055, 0xe940):
return 1;
}
return 0;
}
int
kse_match(unsigned tag, void *data)
{
unsigned v;
v = pcicfgread(tag, PCI_ID_REG);
switch (v) {
case PCI_DEVICE(0x16c6, 0x8841):
case PCI_DEVICE(0x16c6, 0x8842):
return 1;
}
return 0;
}
int
siisata_match(unsigned tag, void *data)
{
unsigned v;
v = pcicfgread(tag, PCI_ID_REG);
switch (v) {
case PCI_DEVICE(0x1095, 0x3112): /* SiI 3112 SATALink */
case PCI_DEVICE(0x1095, 0x3512): /* 3512 SATALink */
case PCI_DEVICE(0x1095, 0x3114): /* SiI 3114 SATALink */
return 1;
}
return 0;
}
u_int
read_board_id(void)
{
uint32_t tag, reg;
#define PCIB_PCI_BUS 0
#define PCIB_PCI_DEV 9
#define PCIB_PCI_FUNC 0
#define PCIB_BOARD_ID_REG 0x94
#define COBALT_BOARD_ID(reg) ((reg & 0x000000f0) >> 4)
tag = (PCIB_PCI_BUS << 16) | (PCIB_PCI_DEV << 11) |
(PCIB_PCI_FUNC << 8);
reg = pcicfgread(tag, PCIB_BOARD_ID_REG);
return COBALT_BOARD_ID(reg);
}
int
pcifinddev(int vid, int did, pcihdl_t *handle)
{
int i;
for (i = 0; i < 32; i++) {
pcihdl_t h;
int id;
h = maketag(0, i, 0);
pcicfgread(&h, 0, &id);
if (id == (vid | (did << 16))) {
*handle = h;
return 0;
}
}
return -1;
}
void *
sme_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned mac32, mac16, val, fdx;
uint8_t *en;
l = ALLOC(struct local, 32); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x1c)); /* BAR3 mem space, LE */
l->phy = 1; /* 9420 internal PHY */
en = data;
mac32 = CSR_READ(l, ADDRL);
mac16 = CSR_READ(l, ADDRH);
en[0] = mac32;
en[1] = mac32 >> 8;
en[2] = mac32 >> 16;
en[3] = mac32 >> 24;
en[4] = mac16;
en[5] = mac16 >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
DPRINTF(("PHY %d (%04x.%04x)\n", l->phy,
mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)));
mii_dealan(l, 5);
/* speed and duplexity can be seen in MII 31 */
val = mii_read(l, l->phy, 31);
fdx = !!(val & (1U << 4));
printf("%s", (val & (1U << 3)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
txd = &l->txd[0];
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(R1_RCH | FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
/* R1_RER neglects xd3 */
l->tx = l->rx = 0;
wbinv(l, sizeof(struct local));
CSR_WRITE(l, TXDBASE, VTOPHYS(txd));
CSR_WRITE(l, RXDBASE, VTOPHYS(rxd));
val = MACCR_TXEN | MACCR_RXEN;
if (fdx)
val |= MACCR_FDPX;
CSR_WRITE(l, BUSMODE, 0);
CSR_WRITE(l, DMACCTL, DMACCTL_ST | DMACCTL_SR);
CSR_WRITE(l, MAC_CR, val); /* (FDX), Tx/Rx enable */
CSR_WRITE(l, RXPOLLD, 01); /* start receiving */
return l;
}
void *
pciide_init(unsigned tag, void *data)
{
static int cntrl = 0;
int native, n, retries;
unsigned val;
struct dkdev_ata *l;
l = alloc(sizeof(struct dkdev_ata));
memset(l, 0, sizeof(struct dkdev_ata));
l->iobuf = allocaligned(512, 16);
l->tag = tag;
/* chipset specific fixes */
if (myops->chipfix)
(*myops->chipfix)(l);
val = pcicfgread(tag, PCI_CLASS_REG);
native = PCI_CLASS(val) != PCI_CLASS_IDE ||
(PCI_INTERFACE(val) & 05) != 0;
if (native) {
/* native, use BAR 01234 */
l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01);
l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
l->chan[0].cmd = l->bar[0];
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
l->chan[0].dma = l->bar[4] + 0x0;
l->chan[1].cmd = l->bar[2];
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
l->chan[1].dma = l->bar[4] + 0x8;
}
else {
/* legacy */
l->bar[0]= pciiobase + 0x1f0;
l->bar[1]= pciiobase + 0x3f4;
l->bar[2]= pciiobase + 0x170;
l->bar[3]= pciiobase + 0x374;
l->chan[0].cmd = l->bar[0];
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
l->chan[0].dma = 0;
l->chan[1].cmd = l->bar[2];
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
l->chan[1].dma = 0;
}
for (n = 0; n < 2; n++) {
if (myops->presense != NULL && (*myops->presense)(l, n) == 0) {
DPRINTF(("channel %d not present\n", n));
l->presense[n] = 0;
continue;
} else if (get_drive_config(cntrl * 2 + n) == 0) {
DPRINTF(("channel %d disabled by config\n", n));
l->presense[n] = 0;
continue;
}
if (atachkpwr(l, n) != ATA_PWR_ACTIVE) {
/* drive is probably sleeping, wake it up */
for (retries = 0; retries < 10; retries++) {
wakeup_drive(l, n);
DPRINTF(("channel %d spinning up...\n", n));
delay(1000 * 1000);
l->presense[n] = perform_atareset(l, n);
if (atachkpwr(l, n) == ATA_PWR_ACTIVE)
break;
}
} else {
/* check to see whether soft reset works */
DPRINTF(("channel %d active\n", n));
l->presense[n] = perform_atareset(l, n);
}
if (l->presense[n])
printf("channel %d present\n", n);
}
cntrl++; /* increment controller number for next call */
return l;
}
int
EtherInit(unsigned char *myadr)
{
uint32_t pcicsr;
uint16_t val;
volatile struct ex_upd *upd;
#ifndef _STANDALONE
uint32_t id;
#endif
if (pcicheck()) {
printf("pcicheck failed\n");
return 0;
}
#ifndef _STANDALONE
pcicfgread(&mytag, 0, &id);
#endif
for (excard = &excards[0]; excard->did != -1; excard++) {
#ifdef _STANDALONE
if (pcifinddev(0x10b7, excard->did, &mytag) == 0)
goto found;
#else
if (id == (0x10b7 | (excard->did << 16)))
goto found;
#endif
}
printf("no ex\n");
return 0;
found:
pcicfgread(&mytag, 0x10, &iobase);
iobase &= ~3;
#ifndef _STANDALONE
dmamem = mapmem(DMABASE, DMASIZE);
if (!dmamem)
return 0;
#endif
/* enable bus mastering in PCI command register */
if (pcicfgread(&mytag, 0x04, (int *)&pcicsr)
|| pcicfgwrite(&mytag, 0x04, pcicsr | 4)) {
printf("cannot enable DMA\n");
return 0;
}
ex_reset();
if (excard->mii)
ether_medium = ETHERMEDIUM_MII;
else {
ex_probemedia();
if (ether_medium < 0)
return 0;
}
val = ex_read_eeprom(EEPROM_OEM_ADDR0);
myethaddr[0] = val >> 8;
myethaddr[1] = val & 0xff;
val = ex_read_eeprom(EEPROM_OEM_ADDR1);
myethaddr[2] = val >> 8;
myethaddr[3] = val & 0xff;
val = ex_read_eeprom(EEPROM_OEM_ADDR2);
myethaddr[4] = val >> 8;
myethaddr[5] = val & 0xff;
memcpy(myadr, myethaddr, 6);
upd = RECVBUF_VIRT;
upd->upd_nextptr = RECVBUF_PHYS;
upd->upd_pktstatus = 1500;
upd->upd_frags[0].fr_addr = RECVBUF_PHYS + 100;
upd->upd_frags[0].fr_len = 1500 | EX_FR_LAST;
ex_init();
#if defined(_STANDALONE) && !defined(SUPPORT_NO_NETBSD)
strncpy(bi_netif.ifname, "ex", sizeof(bi_netif.ifname));
bi_netif.bus = BI_BUS_PCI;
bi_netif.addr.tag = mytag;
BI_ADD(&bi_netif, BTINFO_NETIF, sizeof(bi_netif));
#endif
return 1;
}
void *
siisata_init(unsigned tag, void *data)
{
unsigned idreg;
int n, nchan, retries/*waitforspinup*/;
struct dkdev_ata *l;
l = alloc(sizeof(struct dkdev_ata));
memset(l, 0, sizeof(struct dkdev_ata));
l->iobuf = allocaligned(512, 16);
l->tag = tag;
idreg = pcicfgread(tag, PCI_ID_REG);
l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01);
l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff;
if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) {
/* 3112/3512 */
l->chan[0].cmd = l->bar[0];
l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
l->chan[0].dma = l->bar[4] + 0x0;
l->chan[1].cmd = l->bar[2];
l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
l->chan[1].dma = l->bar[4] + 0x8;
nchan = 2;
}
else {
/* 3114 - assume BA5 access is possible XXX */
l->chan[0].cmd = l->bar[5] + 0x080;
l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02;
l->chan[1].cmd = l->bar[5] + 0x0c0;
l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02;
l->chan[2].cmd = l->bar[5] + 0x280;
l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02;
l->chan[3].cmd = l->bar[5] + 0x2c0;
l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02;
nchan = 4;
}
/* configure PIO transfer mode */
pcicfgwrite(tag, 0x80, 0x00);
pcicfgwrite(tag, 0x84, 0x00);
for (n = 0; n < nchan; n++) {
l->presense[n] = satapresense(l, n);
if (l->presense[n] == 0) {
/* wait some seconds to power-up the drive */
for (retries = 0; retries < sata_delay[n]; retries++) {
wakeup_drive(l, n);
printf("Waiting %2d seconds for powering up "
"port %d.\r", sata_delay[n] - retries, n);
delay(1000 * 1000);
if ((l->presense[n] = satapresense(l, n)) != 0)
break;
}
putchar('\n');
if (l->presense[n] == 0) {
DPRINTF(("port %d not present\n", n));
continue;
}
}
if (atachkpwr(l, n) != ATA_PWR_ACTIVE) {
/* drive is probably sleeping, wake it up */
for (retries = 0; retries < 20; retries++) {
wakeup_drive(l, n);
DPRINTF(("port %d spinning up...\n", n));
delay(1000 * 1000);
l->presense[n] = perform_atareset(l, n);
if (atachkpwr(l, n) == ATA_PWR_ACTIVE)
break;
}
} else {
/* check to see whether soft reset works */
DPRINTF(("port %d active\n", n));
for (retries = 0; retries < 20; retries++) {
l->presense[n] = perform_atareset(l, n);
if (l->presense[n] != 0)
break;
wakeup_drive(l, n);
DPRINTF(("port %d cold-starting...\n", n));
delay(1000 * 1000);
}
}
if (l->presense[n])
printf("port %d present\n", n);
}
return l;
}
