static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801jx_config *config = dev->chip_info; /* Normal PCIe Scan */ pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } }
static void pch_pciexp_scan_bridge(device_t dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); }
static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) { u16 val; u16 ctl; int flag = 0; do { val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); if ((val & (1<<11)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag=1; hard_reset(); } } while (val & (3<<10)); return pciexp_scan_bridge(dev, max); }