/* ---------------------------------------------------------------------------- nmclan_reset Reset and restore all of the Xilinx and MACE registers. ---------------------------------------------------------------------------- */ static void nmclan_reset(struct net_device *dev) { mace_private *lp = netdev_priv(dev); #if RESET_XILINX struct pcmcia_device *link = &lp->link; u8 OrigCorValue; /* Save original COR value */ pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); /* Reset Xilinx */ dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", OrigCorValue); pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); /* Need to wait for 20 ms for PCMCIA to finish reset. */ /* Restore original COR configuration index */ pcmcia_write_config_byte(link, CISREG_COR, (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); /* Xilinx is now completely reset along with the MACE chip. */ lp->tx_free_frames=AM2150_MAX_TX_FRAMES; #endif /* #if RESET_XILINX */ /* Xilinx is now completely reset along with the MACE chip. */ lp->tx_free_frames=AM2150_MAX_TX_FRAMES; /* Reinitialize the MACE chip for operation. */ mace_init(lp, dev->base_addr, dev->dev_addr); mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); /* Restore the multicast list and enable TX and RX. */ restore_multicast_list(dev); } /* nmclan_reset */
static int sandisk_enable_wireless(struct net_device *dev) { int res, ret = 0; struct hostap_interface *iface = netdev_priv(dev); local_info_t *local = iface->local; struct hostap_cs_priv *hw_priv = local->hw_priv; if (resource_size(hw_priv->link->resource[0]) < 0x42) { ret = -ENODEV; goto done; } if (hw_priv->link->manf_id != 0xd601 || hw_priv->link->card_id != 0x0101) { ret = -ENODEV; goto done; } if (hw_priv->link->socket->functions < 2) { ret = -ENODEV; goto done; } printk(KERN_DEBUG "%s: Multi-function SanDisk ConnectPlus detected" " - using vendor-specific initialization\n", dev->name); hw_priv->sandisk_connectplus = 1; res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, COR_SOFT_RESET); if (res != 0) { printk(KERN_DEBUG "%s: SanDisk - COR sreset failed (%d)\n", dev->name, res); goto done; } mdelay(5); res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, (COR_LEVEL_REQ | 0x8 | COR_ADDR_DECODE | COR_FUNC_ENA)); if (res != 0) { printk(KERN_DEBUG "%s: SanDisk - COR sreset failed (%d)\n", dev->name, res); goto done; } mdelay(5); sandisk_set_iobase(local); HFA384X_OUTB(0xc5, SANDISK_WLAN_ACTIVATION_OFF); udelay(10); HFA384X_OUTB(0x4b, SANDISK_WLAN_ACTIVATION_OFF); udelay(10); done: return ret; }
static void prism2_pccard_genesis_reset(local_info_t *local, int hcr) { int res; u8 old_cor; struct hostap_cs_priv *hw_priv = local->hw_priv; if (!prism2_pccard_card_present(local)) return; if (hw_priv->sandisk_connectplus) { sandisk_write_hcr(local, hcr); return; } res = pcmcia_read_config_byte(hw_priv->link, CISREG_COR, &old_cor); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_genesis_sreset failed 1 " "(%d)\n", res); return; } printk(KERN_DEBUG "prism2_pccard_genesis_sreset: original COR %02x\n", old_cor); res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, old_cor | COR_SOFT_RESET); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_genesis_sreset failed 2 " "(%d)\n", res); return; } mdelay(10); /* Setup Genesis mode */ res = pcmcia_write_config_byte(hw_priv->link, CISREG_CCSR, hcr); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_genesis_sreset failed 3 " "(%d)\n", res); return; } mdelay(10); res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, old_cor & ~COR_SOFT_RESET); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_genesis_sreset failed 4 " "(%d)\n", res); return; } mdelay(10); }
/* * Reset the card using configuration registers COR and CCSR. * If IDLE is 1, stop the firmware, so that it can be safely rewritten. */ static int spectrum_reset(struct pcmcia_device *link, int idle) { int ret; u8 save_cor; u8 ccsr; /* Doing it if hardware is gone is guaranteed crash */ if (!pcmcia_dev_present(link)) return -ENODEV; /* Save original COR value */ ret = pcmcia_read_config_byte(link, CISREG_COR, &save_cor); if (ret) goto failed; /* Soft-Reset card */ ret = pcmcia_write_config_byte(link, CISREG_COR, (save_cor | COR_SOFT_RESET)); if (ret) goto failed; udelay(1000); /* Read CCSR */ ret = pcmcia_read_config_byte(link, CISREG_CCSR, &ccsr); if (ret) goto failed; /* * Start or stop the firmware. Memory width bit should be * preserved from the value we've just read. */ ccsr = (idle ? HCR_IDLE : HCR_RUN) | (ccsr & HCR_MEM16); ret = pcmcia_write_config_byte(link, CISREG_CCSR, ccsr); if (ret) goto failed; udelay(1000); /* Restore original COR configuration index */ ret = pcmcia_write_config_byte(link, CISREG_COR, (save_cor & ~COR_SOFT_RESET)); if (ret) goto failed; udelay(1000); return 0; failed: return -ENODEV; }
static int spectrum_reset(struct pcmcia_device *link, int idle) { int ret; u8 save_cor; u8 ccsr; /* */ if (!pcmcia_dev_present(link)) return -ENODEV; /* */ ret = pcmcia_read_config_byte(link, CISREG_COR, &save_cor); if (ret) goto failed; /* */ ret = pcmcia_write_config_byte(link, CISREG_COR, (save_cor | COR_SOFT_RESET)); if (ret) goto failed; udelay(1000); /* */ ret = pcmcia_read_config_byte(link, CISREG_CCSR, &ccsr); if (ret) goto failed; /* */ ccsr = (idle ? HCR_IDLE : HCR_RUN) | (ccsr & HCR_MEM16); ret = pcmcia_write_config_byte(link, CISREG_CCSR, ccsr); if (ret) goto failed; udelay(1000); /* */ ret = pcmcia_write_config_byte(link, CISREG_COR, (save_cor & ~COR_SOFT_RESET)); if (ret) goto failed; udelay(1000); return 0; failed: return -ENODEV; }
static int softingcs_enable_irq(struct platform_device *pdev, int v) { struct pcmcia_device *pcmcia = to_pcmcia_dev(pdev->dev.parent); dev_dbg(&pdev->dev, "pcmcia config [0] %02x\n", v ? 0x60 : 0); return pcmcia_write_config_byte(pcmcia, 0, v ? 0x60 : 0); }
/* * platformdata callbacks */ static int softingcs_reset(struct platform_device *pdev, int v) { struct pcmcia_device *pcmcia = to_pcmcia_dev(pdev->dev.parent); dev_dbg(&pdev->dev, "pcmcia config [2] %02x\n", v ? 0 : 0x20); return pcmcia_write_config_byte(pcmcia, 2, v ? 0 : 0x20); }
static void prism2_pccard_cor_sreset(local_info_t *local) { int res; u8 val; struct hostap_cs_priv *hw_priv = local->hw_priv; if (!prism2_pccard_card_present(local)) return; res = pcmcia_read_config_byte(hw_priv->link, CISREG_COR, &val); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_cor_sreset failed 1 (%d)\n", res); return; } printk(KERN_DEBUG "prism2_pccard_cor_sreset: original COR %02x\n", val); val |= COR_SOFT_RESET; res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, val); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_cor_sreset failed 2 (%d)\n", res); return; } mdelay(hw_priv->sandisk_connectplus ? 5 : 2); val &= ~COR_SOFT_RESET; if (hw_priv->sandisk_connectplus) val |= COR_IREQ_ENA; res = pcmcia_write_config_byte(hw_priv->link, CISREG_COR, val); if (res != 0) { printk(KERN_DEBUG "prism2_pccard_cor_sreset failed 3 (%d)\n", res); return; } mdelay(hw_priv->sandisk_connectplus ? 5 : 2); if (hw_priv->sandisk_connectplus) sandisk_set_iobase(local); }
static void sandisk_set_iobase(local_info_t *local) { int res; struct hostap_cs_priv *hw_priv = local->hw_priv; res = pcmcia_write_config_byte(hw_priv->link, 0x10, hw_priv->link->resource[0]->start & 0x00ff); if (res != 0) { printk(KERN_DEBUG "Prism3 SanDisk - failed to set I/O base 0 -" " res=%d\n", res); } udelay(10); res = pcmcia_write_config_byte(hw_priv->link, 0x12, (hw_priv->link->resource[0]->start >> 8) & 0x00ff); if (res != 0) { printk(KERN_DEBUG "Prism3 SanDisk - failed to set I/O base 1 -" " res=%d\n", res); } }
static int xirc2ps_config(struct pcmcia_device * link) { struct net_device *dev = link->priv; local_info_t *local = netdev_priv(dev); unsigned int ioaddr; int err; u8 *buf; size_t len; local->dingo_ccr = NULL; dev_dbg(&link->dev, "config\n"); if (link->has_manf_id == 0) { pr_notice("manfid not found in CIS\n"); goto failure; } switch (link->manf_id) { case MANFID_XIRCOM: local->manf_str = "Xircom"; break; case MANFID_ACCTON: local->manf_str = "Accton"; break; case MANFID_COMPAQ: case MANFID_COMPAQ2: local->manf_str = "Compaq"; break; case MANFID_INTEL: local->manf_str = "Intel"; break; case MANFID_TOSHIBA: local->manf_str = "Toshiba"; break; default: pr_notice("Unknown Card Manufacturer ID: 0x%04x\n", (unsigned)link->manf_id); goto failure; } dev_dbg(&link->dev, "found %s card\n", local->manf_str); if (!set_card_type(link)) { pr_notice("this card is not supported\n"); goto failure; } err = pcmcia_get_mac_from_cis(link, dev); if (err) { len = pcmcia_get_tuple(link, 0x89, &buf); if (buf && len == 8) { if (*buf == CISTPL_FUNCE_LAN_NODE_ID) { int i; for (i = 2; i < 6; i++) dev->dev_addr[i] = buf[i+2]; } else err = -1; } kfree(buf); } if (err) err = pcmcia_loop_tuple(link, CISTPL_FUNCE, pcmcia_get_mac_ce, dev); if (err) { pr_notice("node-id not found in CIS\n"); goto failure; } if (local->modem) { int pass; link->config_flags |= CONF_AUTO_SET_IO; if (local->dingo) { if (!pcmcia_loop_config(link, xirc2ps_config_modem, NULL)) goto port_found; } else { for (pass=0; pass < 2; pass++) if (!pcmcia_loop_config(link, xirc2ps_config_check, &pass)) goto port_found; } pr_notice("no ports available\n"); } else { link->io_lines = 10; link->resource[0]->end = 16; link->resource[0]->flags |= IO_DATA_PATH_WIDTH_16; for (ioaddr = 0x300; ioaddr < 0x400; ioaddr += 0x10) { link->resource[0]->start = ioaddr; if (!(err = pcmcia_request_io(link))) goto port_found; } link->resource[0]->start = 0; if ((err = pcmcia_request_io(link))) goto config_error; } port_found: if (err) goto config_error; if ((err=pcmcia_request_irq(link, xirc2ps_interrupt))) goto config_error; link->config_flags |= CONF_ENABLE_IRQ; if (do_sound) link->config_flags |= CONF_ENABLE_SPKR; if ((err = pcmcia_enable_device(link))) goto config_error; if (local->dingo) { /* Reset the modem's BAR to the correct value * This is necessary because in the RequestConfiguration call, * the base address of the ethernet port (BasePort1) is written * to the BAR registers of the modem. */ err = pcmcia_write_config_byte(link, CISREG_IOBASE_0, (u8) link->resource[1]->start & 0xff); if (err) goto config_error; err = pcmcia_write_config_byte(link, CISREG_IOBASE_1, (link->resource[1]->start >> 8) & 0xff); if (err) goto config_error; link->resource[2]->flags = WIN_DATA_WIDTH_8 | WIN_MEMORY_TYPE_AM | WIN_ENABLE; link->resource[2]->start = link->resource[2]->end = 0; if ((err = pcmcia_request_window(link, link->resource[2], 0))) goto config_error; local->dingo_ccr = ioremap(link->resource[2]->start, 0x1000) + 0x0800; if ((err = pcmcia_map_mem_page(link, link->resource[2], 0))) goto config_error; writeb(0x47, local->dingo_ccr + CISREG_COR); ioaddr = link->resource[0]->start; writeb(ioaddr & 0xff , local->dingo_ccr + CISREG_IOBASE_0); writeb((ioaddr >> 8)&0xff , local->dingo_ccr + CISREG_IOBASE_1); #if 0 { u_char tmp; pr_info("ECOR:"); for (i=0; i < 7; i++) { tmp = readb(local->dingo_ccr + i*2); pr_cont(" %02x", tmp); } pr_cont("\n"); pr_info("DCOR:"); for (i=0; i < 4; i++) { tmp = readb(local->dingo_ccr + 0x20 + i*2); pr_cont(" %02x", tmp); } pr_cont("\n"); pr_info("SCOR:"); for (i=0; i < 10; i++) { tmp = readb(local->dingo_ccr + 0x40 + i*2); pr_cont(" %02x", tmp); } pr_cont("\n"); } #endif writeb(0x01, local->dingo_ccr + 0x20); writeb(0x0c, local->dingo_ccr + 0x22); writeb(0x00, local->dingo_ccr + 0x24); writeb(0x00, local->dingo_ccr + 0x26); writeb(0x00, local->dingo_ccr + 0x28); }