static int pfuze100_init(struct mc_pfuze *pfuze) { int ret; unsigned int reg; if (arm_max_freq == CPU_AT_1_2GHz) { /*VDDARM_IN 1.475V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, PFUZE100_SW1AVOL_VSEL_M, 0x2f); if (ret) goto err; /*VDDSOC_IN 1.475V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL, PFUZE100_SW1CVOL_VSEL_M, 0x2f); if (ret) goto err; /*set VDDSOC&VDDPU to 1.25V*/ reg = __raw_readl(ANADIG_REG_CORE); reg &= ~BM_ANADIG_REG_CORE_REG2_TRG; reg |= BF_ANADIG_REG_CORE_REG2_TRG(0x16); reg &= ~BM_ANADIG_REG_CORE_REG1_TRG; reg |= BF_ANADIG_REG_CORE_REG1_TRG(0x16); __raw_writel(reg, ANADIG_REG_CORE); } ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, PFUZE100_SW1ASTANDBY_STBY_M, PFUZE100_SW1ASTANDBY_STBY_VAL); if (ret) goto err; ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, PFUZE100_SW1CSTANDBY_STBY_M, PFUZE100_SW1CSTANDBY_STBY_VAL); if (ret) goto err; /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, PFUZE100_SW1ACON_SPEED_M, PFUZE100_SW1ACON_SPEED_VAL); if (ret) goto err; ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON, PFUZE100_SW1CCON_SPEED_M, PFUZE100_SW1CCON_SPEED_VAL); if (ret) goto err; return 0; err: printk(KERN_ERR "pfuze100 init error!\n"); return -1; }
static int pfuze100_init(struct mc_pfuze *pfuze) { int ret, i; unsigned char value; /*use default mode(ldo bypass) if no param from cmdline*/ if (enable_ldo_mode == LDO_MODE_DEFAULT) enable_ldo_mode = LDO_MODE_BYPASSED; /*read Device ID*/ ret = pfuze_reg_read(pfuze, PFUZE100_DEVICEID, &value); if (ret) goto err; if (value != 0x10) { printk(KERN_ERR "wrong device id:%x!\n", value); goto err; } /*read Revision ID*/ ret = pfuze_reg_read(pfuze, PFUZE100_REVID, &value); if (ret) goto err; if (value == 0x10) { printk(KERN_WARNING "PF100 1.0 chip found!\n"); /* workaround ER1 of pfuze1.0: set all buck regulators in PWM mode * except SW1C(APS) in normal and PFM mode in standby. */ for (i = 0; i < 7; i++) { if (i == 2)/*SW1C*/ value = 0xc;/*normal:APS mode;standby:PFM mode*/ else value = 0xd;/*normal:PWM mode;standby:PFM mode*/ ret = pfuze_reg_write(pfuze, PFUZE100_SW1AMODE + (i * 7), value); if (ret) goto err; } } else { /*set all switches APS in normal and PFM mode in standby*/ for (i = 0; i < 7; i++) { value = 0xc; ret = pfuze_reg_write(pfuze, PFUZE100_SW1AMODE + (i * 7), value); if (ret) goto err; } } /*use ldo active mode if use 1.2GHz,otherwise use ldo bypass mode*/ if (arm_max_freq == CPU_AT_1_2GHz) { /*VDDARM_IN 1.425*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, PFUZE100_SW1AVOL_VSEL_M, 0x2d); if (ret) goto err; /*VDDSOC_IN 1.425V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL, PFUZE100_SW1CVOL_VSEL_M, 0x2d); if (ret) goto err; enable_ldo_mode = LDO_MODE_ENABLED; } else if (enable_ldo_mode == LDO_MODE_BYPASSED) { /*decrease VDDARM_IN/VDDSOC_IN,since we will use ldo bypass mode*/ /*VDDARM_IN 1.3V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, PFUZE100_SW1AVOL_VSEL_M, 0x28); if (ret) goto err; /*VDDSOC_IN 1.3V*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL, PFUZE100_SW1CVOL_VSEL_M, 0x28); if (ret) goto err; /*set SW1AB/1C DVSPEED as 25mV step each 4us,quick than 16us before.*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ACON, PFUZE100_SW1ACON_SPEED_M, PFUZE100_SW1ACON_SPEED_VAL); if (ret) goto err; ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CCON, PFUZE100_SW1CCON_SPEED_M, PFUZE100_SW1CCON_SPEED_VAL); if (ret) goto err; } else if (enable_ldo_mode != LDO_MODE_BYPASSED) { /*Increase VDDARM_IN/VDDSOC_IN to 1.375V in ldo active mode*/ ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1AVOL, PFUZE100_SW1AVOL_VSEL_M, 0x2b); if (ret) goto err; ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CVOL, PFUZE100_SW1CVOL_VSEL_M, 0x2b); if (ret) goto err; } return 0; err: printk(KERN_ERR "pfuze100 init error!\n"); return -1; }