static void s11_irqline(int state) { if (state) { cpu_set_irq_line(0, M6808_IRQ_LINE, ASSERT_LINE); /*Set coin door inputs, differs between S11 & DE*/ if (locals.deGame) { pia_set_input_ca1(S11_PIA2, !core_getSw(DE_SWADVANCE)); pia_set_input_cb1(S11_PIA2, core_getSw(DE_SWUPDN)); } else { pia_set_input_ca1(S11_PIA2, core_getSw(S11_SWADVANCE)); pia_set_input_cb1(S11_PIA2, core_getSw(S11_SWUPDN)); } } else if (!locals.piaIrq) { cpu_set_irq_line(0, M6808_IRQ_LINE, CLEAR_LINE); pia_set_input_ca1(S11_PIA2, locals.deGame); pia_set_input_cb1(S11_PIA2, locals.deGame); } }
static SWITCH_UPDATE(allied) { if (inports) { CORE_SETKEYSW(inports[CORE_COREINPORT] & 0x80, 0x80, 4); CORE_SETKEYSW(inports[CORE_COREINPORT] >> 8, 0x1f, 5); } locals.test = (coreGlobals.swMatrix[5] & 0x10) ? 0 : 1; // J2-W (credit) pia_set_input_cb1(ALI_IC4, (coreGlobals.swMatrix[4] & 0x80) ? 0 : 1); // J2-20/X (coin 3) locals.coin[0] = (coreGlobals.swMatrix[5] & 0x02) ? 0 : 1; pia_set_input_ca1(ALI_IC8, locals.coin[0]); // J2-21/Y (coin 2) locals.coin[1] = (coreGlobals.swMatrix[5] & 0x04) ? 0 : 1; pia_set_input_cb1(ALI_IC8, locals.coin[1]); // J2-22/Z (coin 1) locals.coin[2] = (coreGlobals.swMatrix[5] & 0x08) ? 0 : 1; pia_set_input_ca2(ALI_IC8, locals.coin[2]); // J1-16 / J2-b (slam) locals.slam = (coreGlobals.swMatrix[5] & 0x01) ? 0 : 1; pia_set_input_cb1(ALI_IC7, locals.slam); pia_set_input_cb2(ALI_IC8, locals.slam); }
void pia_6_ca1_w (int offset, int data) { pia_set_input_ca1 (5, data); }
void pia_5_ca1_w (int offset, int data) { pia_set_input_ca1 (4, data); }
void pia_4_ca1_w (int offset, int data) { pia_set_input_ca1 (3, data); }
void pia_3_ca1_w (int offset, int data) { pia_set_input_ca1 (2, data); }
void pia_2_ca1_w (int offset, int data) { pia_set_input_ca1 (1, data); }
void pia_1_ca1_w (int offset, int data) { pia_set_input_ca1 (0, data); }
static WRITE_HANDLER(s11s_manCmd_w) { soundlatch_w(0, data); pia_set_input_ca1(S11S_PIA0, 1); pia_set_input_ca1(S11S_PIA0, 0); }
int pia_read(int which, int offset) { struct pia6821 *p = pia + which; int val = 0; /* adjust offset for 16-bit and ordering */ offset &= 3; if (p->addr & PIA_ALTERNATE_ORDERING) offset = swizzle_address[offset]; switch (offset) { /******************* port A output/DDR read *******************/ case PIA_DDRA: /* read output register */ if (OUTPUT_SELECTED(p->ctl_a)) { /* update the input */ if ((FPTR)(p->intf->in_a_func) > 0x100) p->in_a = p->intf->in_a_func(0); #ifdef MAME_DEBUG else if ((p->ddr_a ^ 0xff) && !(p->in_set & PIA_IN_SET_A)) { logerror("PIA%d: Warning! no port A read handler. Assuming pins %02x not connected\n", which, p->ddr_a ^ 0xff); p->in_set |= PIA_IN_SET_A; // disable logging } #endif // MAME_DEBUG /* combine input and output values */ val = (p->out_a & p->ddr_a) + (p->in_a & ~p->ddr_a); /* IRQ flags implicitly cleared by a read */ p->irq_a1 = p->irq_a2 = 0; update_6821_interrupts(p); /* CA2 is configured as output and in read strobe mode */ if (C2_OUTPUT(p->ctl_a) && C2_STROBE_MODE(p->ctl_a)) { /* this will cause a transition low; call the output function if we're currently high */ if (p->out_ca2) if (p->intf->out_ca2_func) p->intf->out_ca2_func(0, 0); p->out_ca2 = 0; /* if the CA2 strobe is cleared by the E, reset it right away */ if (STROBE_E_RESET(p->ctl_a)) { if (p->intf->out_ca2_func) p->intf->out_ca2_func(0, 1); p->out_ca2 = 1; } } LOG(("%04x: PIA%d read port A = %02X\n", activecpu_get_previouspc(), which, val)); } /* read DDR register */ else { val = p->ddr_a; LOG(("%04x: PIA%d read DDR A = %02X\n", activecpu_get_previouspc(), which, val)); } break; /******************* port B output/DDR read *******************/ case PIA_DDRB: /* read output register */ if (OUTPUT_SELECTED(p->ctl_b)) { /* update the input */ if ((FPTR)(p->intf->in_b_func) > 0x100) p->in_b = p->intf->in_b_func(0); #ifdef MAME_DEBUG else if ((p->ddr_b ^ 0xff) && !(p->in_set & PIA_IN_SET_B)) { logerror("PIA%d: Error! no port B read handler. Three-state pins %02x are undefined\n", which, p->ddr_b ^ 0xff); p->in_set |= PIA_IN_SET_B; // disable logging } #endif // MAME_DEBUG /* combine input and output values */ val = (p->out_b & p->ddr_b) + (p->in_b & ~p->ddr_b); /* IRQ flags implicitly cleared by a read */ p->irq_b1 = p->irq_b2 = 0; update_6821_interrupts(p); LOG(("%04x: PIA%d read port B = %02X\n", activecpu_get_previouspc(), which, val)); } /* read DDR register */ else { val = p->ddr_b; LOG(("%04x: PIA%d read DDR B = %02X\n", activecpu_get_previouspc(), which, val)); } break; /******************* port A control read *******************/ case PIA_CTLA: /* Update CA1 & CA2 if callback exists, these in turn may update IRQ's */ if ((FPTR)(p->intf->in_ca1_func) > 0x100) pia_set_input_ca1(which, p->intf->in_ca1_func(0)); #ifdef MAME_DEBUG else if (!(p->in_set & PIA_IN_SET_CA1)) { logerror("PIA%d: Warning! no CA1 read handler. Assuming pin not connected\n",which); p->in_set |= PIA_IN_SET_CA1; // disable logging } #endif // MAME_DEBUG if ((FPTR)(p->intf->in_ca2_func) > 0x100) pia_set_input_ca2(which, p->intf->in_ca2_func(0)); #ifdef MAME_DEBUG else if (C2_INPUT(p->ctl_a) && !(p->in_set & PIA_IN_SET_CA2)) { logerror("PIA%d: Warning! no CA2 read handler. Assuming pin not connected\n",which); p->in_set |= PIA_IN_SET_CA2; // disable logging } #endif // MAME_DEBUG /* read control register */ val = p->ctl_a; /* set the IRQ flags if we have pending IRQs */ if (p->irq_a1) val |= PIA_IRQ1; if (p->irq_a2 && C2_INPUT(p->ctl_a)) val |= PIA_IRQ2; LOG(("%04x: PIA%d read control A = %02X\n", activecpu_get_previouspc(), which, val)); break; /******************* port B control read *******************/ case PIA_CTLB: /* Update CB1 & CB2 if callback exists, these in turn may update IRQ's */ if ((FPTR)(p->intf->in_cb1_func) > 0x100) pia_set_input_cb1(which, p->intf->in_cb1_func(0)); #ifdef MAME_DEBUG else if (!(p->in_set & PIA_IN_SET_CB1)) { logerror("PIA%d: Error! no CB1 read handler. Three-state pin is undefined\n",which); p->in_set |= PIA_IN_SET_CB1; // disable logging } #endif // MAME_DEBUG if ((FPTR)(p->intf->in_cb2_func) > 0x100) pia_set_input_cb2(which, p->intf->in_cb2_func(0)); #ifdef MAME_DEBUG else if (C2_INPUT(p->ctl_b) && !(p->in_set & PIA_IN_SET_CB2)) { logerror("PIA%d: Error! no CB2 read handler. Three-state pin is undefined\n",which); p->in_set |= PIA_IN_SET_CB2; // disable logging } #endif // MAME_DEBUG /* read control register */ val = p->ctl_b; /* set the IRQ flags if we have pending IRQs */ if (p->irq_b1) val |= PIA_IRQ1; if (p->irq_b2 && C2_INPUT(p->ctl_b)) val |= PIA_IRQ2; LOG(("%04x: PIA%d read control B = %02X\n", activecpu_get_previouspc(), which, val)); break; } return val; }
static void apple1_kbd_strobe_end(int dummy) { /* End of the keyboard strobe pulse. */ pia_set_input_ca1(0, 0); }
/***************************************************************************** ** apple1_kbd_poll ** ** Keyboard polling handles both ordinary keys and the special RESET ** and CLEAR SCREEN switches. ** ** For ordinary keys, this implements 2-key rollover to reduce the ** chance of missed keypresses. If we press a key and then press a ** second key while the first hasn't been completely released, as ** might happen during rapid typing, only the second key is ** registered; the first key is ignored. ** ** If multiple newly-pressed keys are found, the one closest to the ** end of the input ports list is counted; the others are ignored. *****************************************************************************/ static void apple1_kbd_poll(int dummy) { int port, bit; int key_pressed; UINT32 shiftkeys, ctrlkeys; /* This holds the values of all the input ports for ordinary keys seen during the last scan. */ static UINT32 kbd_last_scan[] = { 0, 0, 0, 0 }; static int reset_flag = 0; /* First we check the RESET and CLEAR SCREEN pushbutton switches. */ /* The RESET switch resets the CPU and the 6820 PIA. */ if (readinputport(5) & 0x0001) { if (!reset_flag) { reset_flag = 1; /* using PULSE_LINE does not allow us to press and hold key */ cpunum_set_input_line(0, INPUT_LINE_RESET, ASSERT_LINE); pia_reset(); } } else if (reset_flag) { /* RESET released--allow the processor to continue. */ reset_flag = 0; cpunum_set_input_line(0, INPUT_LINE_RESET, CLEAR_LINE); } /* The CLEAR SCREEN switch clears the video hardware. */ if (readinputport(5) & 0x0002) { if (!apple1_vh_clrscrn_pressed) { /* Ignore further video writes, and clear the screen. */ apple1_vh_clrscrn_pressed = 1; apple1_vh_dsp_clr(); } } else if (apple1_vh_clrscrn_pressed) { /* CLEAR SCREEN released--pay attention to video writes again. */ apple1_vh_clrscrn_pressed = 0; } /* Now we scan all the input ports for ordinary keys, recording new keypresses while ignoring keys that were already pressed in the last scan. */ apple1_kbd_data = 0; key_pressed = 0; /* The keyboard strobe line should always be low when a scan starts. */ pia_set_input_ca1(0, 0); shiftkeys = readinputport(4) & 0x0003; ctrlkeys = readinputport(4) & 0x000c; for (port = 0; port < 4; port++) { UINT32 portval = readinputport(port); UINT32 newkeys = portval & ~(kbd_last_scan[port]); if (newkeys) { key_pressed = 1; for (bit = 0; bit < 16; bit++) { if (newkeys & 1) { apple1_kbd_data = (ctrlkeys) ? apple1_control_keymap[port*16 + bit] : (shiftkeys) ? apple1_shifted_keymap[port*16 + bit] : apple1_unshifted_keymap[port*16 + bit]; } newkeys >>= 1; } } kbd_last_scan[port] = portval; } if (key_pressed) { /* The keyboard will pulse its strobe line when a key is pressed. A 10-usec pulse is typical. */ pia_set_input_ca1(0, 1); timer_set(TIME_IN_USEC(10), 0, apple1_kbd_strobe_end); } }
static WRITE_HANDLER(ext_hs_w) { pia_set_input_ca1(S9P_PIA0, data); }
static WRITE_HANDLER(s9p_hs_w) { pia_set_input_ca1(0, data); }
void pia_7_ca1_w (int offset, int data) { pia_set_input_ca1 (6, data); }
void pia_8_ca1_w (int offset, int data) { pia_set_input_ca1 (7, data); }
int pia_read (int which, int offset) { struct pia6821 *p = pia + which; int val = 0; switch (pia_offsets[offset & 7]) { /******************* port A output/DDR read *******************/ case 0: /* read output register */ if (OUTPUT_SELECTED (p->ctl_a)) { /* update the input */ if (p->in_a_func) p->in_a = p->in_a_func (0); /* combine input and output values */ val = (p->out_a & p->ddr_a) + (p->in_a & ~p->ddr_a); /* IRQ flags implicitly cleared by a read */ p->irq_a1 = p->irq_a2 = 0; /* CA2 is configured as output and in read strobe mode */ if (C2_OUTPUT (p->ctl_a) && C2_STROBE_MODE (p->ctl_a)) { /* this will cause a transition low; call the output function if we're currently high */ if (p->out_ca2) if (p->out_ca2_func) p->out_ca2_func (0, 0); p->out_ca2 = 0; /* if the CA2 strobe is cleared by the E, reset it right away */ if (STROBE_E_RESET (p->ctl_a)) { if (p->out_ca2_func) p->out_ca2_func (0, 1); p->out_ca2 = 1; } } } /* read DDR register */ else val = p->ddr_a; break; /******************* port B output/DDR read *******************/ case 1: /* read output register */ if (OUTPUT_SELECTED (p->ctl_b)) { /* update the input */ if (p->in_b_func) p->in_b = p->in_b_func (0); /* combine input and output values */ val = (p->out_b & p->ddr_b) + (p->in_b & ~p->ddr_b); /* IRQ flags implicitly cleared by a read */ p->irq_b1 = p->irq_b2 = 0; } /* read DDR register */ else val = p->ddr_b; break; /******************* port A control read *******************/ case 2: /* Update CA1 & CA2 if callback exists, these in turn may update IRQ's */ if (p->in_ca1_func) pia_set_input_ca1(which, p->in_ca1_func (0)); if (p->in_ca2_func) pia_set_input_ca2(which, p->in_ca2_func (0)); /* read control register */ val = p->ctl_a; /* set the IRQ flags if we have pending IRQs */ if (p->irq_a1) val |= PIA_IRQ1; if (p->irq_a2 && C2_INPUT (p->ctl_a)) val |= PIA_IRQ2; break; /******************* port B control read *******************/ case 3: /* Update CB1 & CB2 if callback exists, these in turn may update IRQ's */ if (p->in_cb1_func) pia_set_input_cb1(which, p->in_cb1_func (0)); if (p->in_cb2_func) pia_set_input_cb2(which, p->in_cb2_func (0)); /* read control register */ val = p->ctl_b; /* set the IRQ flags if we have pending IRQs */ if (p->irq_b1) val |= PIA_IRQ1; if (p->irq_b2 && C2_INPUT (p->ctl_b)) val |= PIA_IRQ2; break; } return val; }