void update(int how)
{
calc_paras(ww,hh,xres,yres);
change_rsc();
set_vcdata(pl_idx,1);
if (how) {
schreib_regs(vcreg,ccreg,xcreg,mcreg);
#if VERSION==PLL_VERSION
if (tree1[MONM2].ob_state&SELECTED)
{old_ww=ww;old_hh=hh;
c_frequ=pll_calc(clock_Mhz,old_ww,old_hh);
}
#endif
}
if (how<2){
/*R objc_draw(tree1,ROOTSCR,10,cx,cy,cw,ch);*/
objc_draw(tree1,HFREQU,10,cx,cy,cw,ch);
objc_draw(tree1,VFREQU,10,cx,cy,cw,ch);
objc_draw(tree1,FESLIDER,10,cx,cy,cw,ch);
objc_draw(tree1,LESLIDER,10,cx,cy,cw,ch);
objc_draw(tree1,WIDTH,10,cx,cy,cw,ch);
objc_draw(tree1,HEIGHT,10,cx,cy,cw,ch);
}
}
/*
* set_freq(uint32_t freq, uint32_t pll_freq, enum si5351_clock output)
*
* Sets the clock frequency of the specified CLK output
*
* freq - Output frequency in Hz
* pll_freq - Frequency of the PLL driving the Multisynth
* Use a 0 to have the function choose a PLL frequency
* clk - Clock output
* (use the si5351_clock enum)
*/
void Si5351::set_freq(uint32_t freq, uint32_t pll_freq, enum si5351_clock clk)
{
struct Si5351RegSet ms_reg, pll_reg;
enum si5351_pll target_pll;
uint8_t set_pll = 0;
/* Calculate the synth parameters */
/* If pll_freq is 0, let the algorithm pick a PLL frequency */
if(pll_freq == 0)
{
pll_freq = multisynth_calc(freq, &ms_reg);
set_pll = 1;
}
/* TODO: bounds checking */
else
{
multisynth_recalc(freq, pll_freq, &ms_reg);
set_pll = 0;
}
/* Determine which PLL to use */
/* CLK0 gets PLLA, CLK1 gets PLLB */
/* CLK2 gets PLLB if necessary */
/* Only good for Si5351A3 variant at the moment */
if(clk == SI5351_CLK0)
{
target_pll = SI5351_PLLA;
si5351_set_ms_source(SI5351_CLK0, SI5351_PLLA);
plla_freq = pll_freq;
}
else if(clk == SI5351_CLK1)
{
target_pll = SI5351_PLLB;
si5351_set_ms_source(SI5351_CLK1, SI5351_PLLB);
pllb_freq = pll_freq;
}
else
{
/* need to account for CLK2 set before CLK1 */
if(pllb_freq == 0)
{
target_pll = SI5351_PLLB;
si5351_set_ms_source(SI5351_CLK2, SI5351_PLLB);
pllb_freq = pll_freq;
}
else
{
target_pll = SI5351_PLLB;
si5351_set_ms_source(SI5351_CLK2, SI5351_PLLB);
pll_freq = pllb_freq;
multisynth_recalc(freq, pll_freq, &ms_reg);
}
}
pll_calc(pll_freq, &pll_reg, ref_correction);
/* Derive the register values to write */
/* Prepare an array for parameters to be written to */
uint8_t *params = new uint8_t[20];
uint8_t i = 0;
uint8_t temp;
/* PLL parameters first */
if(set_pll == 1)
{
/* Registers 26-27 */
temp = ((pll_reg.p3 >> 8) & 0xFF);
params[i++] = temp;
temp = (uint8_t)(pll_reg.p3 & 0xFF);
params[i++] = temp;
/* Register 28 */
temp = (uint8_t)((pll_reg.p1 >> 16) & 0x03);
params[i++] = temp;
/* Registers 29-30 */
temp = (uint8_t)((pll_reg.p1 >> 8) & 0xFF);
params[i++] = temp;
temp = (uint8_t)(pll_reg.p1 & 0xFF);
params[i++] = temp;
/* Register 31 */
temp = (uint8_t)((pll_reg.p3 >> 12) & 0xF0);
temp += (uint8_t)((pll_reg.p2 >> 16) & 0x0F);
params[i++] = temp;
/* Registers 32-33 */
temp = (uint8_t)((pll_reg.p2 >> 8) & 0xFF);
params[i++] = temp;
temp = (uint8_t)(pll_reg.p2 & 0xFF);
params[i++] = temp;
/* Write the parameters */
if(target_pll == SI5351_PLLA)
{
si5351_write_bulk(SI5351_PLLA_PARAMETERS, i + 1, params);
}
else if(target_pll == SI5351_PLLB)
{
si5351_write_bulk(SI5351_PLLB_PARAMETERS, i + 1, params);
}
}
