static int sys_pwr_domain_resume(void) { pmu_sgrf_rst_hld(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); plls_resume(); mmio_write_32(PMU_BASE + PMU_CCI500_CON, WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | WMSK_BIT(PMU_QGATING_CCI500_CFG)); mmio_write_32(PMU_BASE + PMU_ADB400_CON, WMSK_BIT(PMU_CLR_CORE_L_HW) | WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); mmio_write_32(PMU_BASE + PMU_ADB400_CON, WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); pmu_scu_b_pwrup(); plat_rockchip_gic_cpuif_enable(); return 0; }
void pm_plls_resume(void) { plls_resume(); mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); }