/* \brief This is an example that shows:
* - how to configure OSC0
* - how to set the main clock to use OSC0 as input
* - how to configure a generic clock GCLK to use OSC0 as input
* - how to output a generic clock to a pin (GLCK_0_1 for EVK1100 or GCLK_2 for
* EVK1101 or GLCK_1_0 for EVK1104+UC3_A3_XPLAINED or GLCK_1_0 for STK600+RCUC3L0
or GLCK_0 for STK600+RCUC3D)
* - how to go into a sleep mode (while still maintaining GCLK output)
*
*/
int main(void)
{
volatile avr32_pm_t* pm = &AVR32_PM;
#if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK ) || (BOARD == STK600_RCUC3D)
// Note: for UC3 C, D and L series, the osc configurations are handled by the SCIF module
// and the synchronous clocks used to clock the main digital logic are handled
// by the PM module.
// 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// 2) Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// 3) Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
#else
// 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
pm_enable_osc0_crystal(pm, FOSC0);
// 2) Enable the OSC0
pm_enable_clk0(pm, OSC0_STARTUP);
// 3) Set the main clock source as being OSC0.
pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);
#endif
// - Configure a generic clock GCLK to use OSC0 as input
// - Output that generic clock to a pin
local_enable_gclk_on_gpio(pm);
//*** Sleep mode
// If there is a chance that any PB write operations are incomplete, the CPU
// should perform a read operation from any register on the PB bus before
// executing the sleep instruction.
AVR32_INTC.ipr[0]; // Dummy read
// - Go into a sleep mode (while still maintaining GCLK output)
SLEEP(AVR32_PM_SMODE_FROZEN);
while (true);
}
int main()
{
pm_enable_osc0_crystal (&AVR32_PM, FOSC0);
pm_enable_clk0 (&AVR32_PM, OSC0_STARTUP);
pm_switch_to_clock (&AVR32_PM, AVR32_PM_MCSEL_OSC0);
USART_Initialize ();
usart_write_line (&AVR32_USART0, "USART initialized\n");
usart_write_line (&AVR32_USART0, "DIP204 initialized\n");
Item_Available_Count = xSemaphoreCreateCounting (Item_Buffer_Count, 0);
Space_Available_Count = xSemaphoreCreateCounting (Item_Buffer_Count, Item_Buffer_Count - 1);
xTaskCreate (Producer_Task_Function, "Producer", 512, NULL, tskIDLE_PRIORITY + 4, &Producer_Task_Handle);
xTaskCreate (Consumer_Task_Function, "Consumer", 512, NULL, tskIDLE_PRIORITY + 4, &Consumer_Task_Handle);
xTaskCreate (Blinker_Task_Function, "Blinker", 512, NULL, tskIDLE_PRIORITY + 4, NULL);
vTaskStartScheduler ();
}
void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
{
pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode
pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
}
void board_init(void)
{
// first change to OSC0 (12MHz)
pm_enable_osc0_crystal(& AVR32_PM, FOSC0); // Enable the Osc0 in crystal mode
pm_enable_clk0(& AVR32_PM, OSC0_STARTUP); // Crystal startup time
pm_switch_to_clock(& AVR32_PM, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
pm_enable_osc1_ext_clock(& AVR32_PM); // ocs1 is external clock
pm_enable_clk1(& AVR32_PM, OSC1_STARTUP);
pm_pll_setup(&AVR32_PM
, 0 // pll
, 3 // mul
, 0 // div -> f_vfo = 16.384 MHz * 8 = 131.072 MHz
, 1 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
, 1 // pll_freq (f_vfo range 80MHz - 180 MHz)
, 1 // pll_div2 (f_pll1 = f_vfo / 2)
, 0 // pll_wbwdisable
);
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
pm_cksel(&AVR32_PM
, 1, 1 // PBA (CPU / 4) = 16.384 MHz
, 0, 0 // PBB 65.536 MHz
, 0, 0 // HSB = CPU 65.536 MHz
);
flashc_set_wait_state(1); // one wait state if CPU clock > 33 MHz
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); // switch to PLL0
// --------------------------------------
// USB clock
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
// --------------------------------------
// LCD display
gpio_enable_gpio( lcd_gpio_map, sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] ) );
int i;
for (i=0; i < (sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] )); i++)
{
gpio_configure_pin( lcd_gpio_map[i].pin, lcd_gpio_map[i].function);
}
gpio_enable_module( lcd_pwm_gpio_map, sizeof( lcd_pwm_gpio_map ) / sizeof( lcd_pwm_gpio_map[0] ) );
// Backlight
AVR32_PWM.channel[6].CMR.cpre = 3;
AVR32_PWM.channel[6].cprd = 1000;
AVR32_PWM.channel[6].cdty = 500;
AVR32_PWM.ENA.chid6 = 1;
// contrast
AVR32_PWM.channel[0].CMR.cpre = 3;
AVR32_PWM.channel[0].cprd = 1000;
AVR32_PWM.channel[0].cdty = 520;
AVR32_PWM.ENA.chid0 = 1;
// switches
gpio_enable_gpio( switch_gpio_map, sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] ) );
for (i=0; i < (sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] )); i++)
{
gpio_configure_pin( switch_gpio_map[i].pin, switch_gpio_map[i].function);
}
// USART
gpio_enable_module( usart_gpio_map, sizeof( usart_gpio_map ) / sizeof( usart_gpio_map[0] ) );
}
