/*! \brief Initializes the MCU system clocks.
*/
void init_sys_clocks(void)
{
// Switch to OSC0 to speed up the booting
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Start oscillator1
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set PLL0 (fed from OSC0 = 12 MHz) to 132 MHz
// We use OSC1 since we need a correct master clock for the SSC module to generate
// the correct sample rate
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
0, // osc.
16); // lockcount.
// Set PLL operating range and divider (fpll = fvco/2)
// -> PLL0 output = 66 MHz
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL0 and wait for the lock
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
// Set all peripheral clocks torun at master clock rate
// Set one waitstate for the flash
flashc_set_wait_state(1);
// Switch to PLL0 as the master clock
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
}
void inicializa_PM(void)
{
// Activa el oscilador Osc0
pm_switch_to_osc0(&AVR32_PM,12000000,6);
//_______________________________________________________________________________
//Establece la frecuencia del VCO
//Si DIV>1 Fvco=((MUL+1)/DIV)*Fosc
//Si DIV=0 Fvco=2*(MUL+1)*Fosc
pm_pll_setup(&AVR32_PM,0,7,0,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,1,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
}
void systemInit(void)
{
//Low-level initialization
_init_startup();
//Switch main clock to OSC0 (12MHz)
pm_switch_to_osc0(&AVR32_PM, OSC0_FREQ, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);
//Start OSC1 (11.2896MHz)
pm_enable_osc1_crystal(&AVR32_PM, OSC1_FREQ);
pm_enable_clk1(&AVR32_PM, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);
//Configure PLL0 (132MHz)
pm_pll_setup(&AVR32_PM, 0, 10, 1, 0, 16);
//Set PLL operating range (80 to 180MHz) and output divider (2)
pm_pll_set_option(&AVR32_PM, 0, 1, 1, 0);
//Start PLL0
pm_pll_enable(&AVR32_PM, 0);
//Wait for the PLL to lock
pm_wait_for_pll0_locked(&AVR32_PM);
//Set FLASH wait-state
flashc_set_wait_state(1);
//Switch main clock to PLL0
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
//Configure PLL1 (96MHz)
pm_pll_setup(&AVR32_PM, 1, 7, 1, 0, 16);
//Set PLL operating range (80 to 180MHz) and output divider (2)
pm_pll_set_option(&AVR32_PM, 1, 1, 1, 0);
//Start PLL1
pm_pll_enable(&AVR32_PM, 1);
//Wait for the PLL to lock
pm_wait_for_pll1_locked(&AVR32_PM);
//Set clock dividers for PBA, PBB and HSB clocks
pm_cksel(&AVR32_PM, 0, 0, 0, 0, 0, 0);
//Initialize SDRAM memory
sdramc_init(HSB_FREQ);
}
/*! \brief Initializes the MCU system clocks.
*/
static void init_sys_clocks(void)
{
// Switch to OSC0 to speed up the booting
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Start oscillator1
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
//
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set PLL0 (fed from OSC1 = 11.2896 MHz) to 112.896 MHz
// We use OSC1 since we need a correct master clock for the SSC module to generate
// the correct sample rate
pm_pll_setup(&AVR32_PM, 0, // pll.
SYS_CLOCK_PLL_MUL-1, // mul.
1, // div.
1, // osc.
16); // lockcount.
// Set PLL operating range and divider (fpll = fvco/2)
// -> PLL0 output = 62.0928 MHz
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL0 and wait for the lock
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
// Set all peripheral clocks torun at master clock rate
pm_cksel(&AVR32_PM,
0, // pbadiv.
0, // pbasel.
0, // pbbdiv.
0, // pbbsel.
0, // hsbdiv.
0); // hsbsel.
// Set one waitstate for the flash
flashc_set_wait_state(1);
// Switch to PLL0 as the master clock
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
#if (defined USB_RESYNC_METHOD) && (USB_RESYNC_METHOD == USB_RESYNC_METHOD_EXT_CLOCK_SYNTHESIZER)
// Holds frequencies parameters
g_fcpu_hz = g_fhsb_hz = g_fpba_hz = g_fpbb_hz = FMCK_HZ(11289600);
#endif
#if (defined __GNUC__) && (defined __AVR32__)
// Give the used PBA clock frequency to Newlib, so it can work properly.
set_cpu_hz(FPBA_HZ);
#endif
init_usb_clock();
init_codec_gclk();
}
void Avr32InitClockTree( void )
{
uint32_t CPUFrequency;
/* Switch main clock to Oscillator 0 */
pm_switch_to_osc0(OSC0_VAL, AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC);
pm_pll_setup(&AVR32_PM, 0, /* use PLL0 */
PLL_MUL_VAL, /* MUL */
PLL_DIV_VAL, /* DIV */
0, /* Oscillator 0 */
16); /* lockcount in main clock for the PLL wait lock */
/*
* This function will set a PLL option.
*
* pm Base address of the Power Manager (i.e. &AVR32_PM)
* pll PLL number 0
* pll_freq Set to 1 for VCO frequency range 80-180MHz,
* set to 0 for VCO frequency range 160-240Mhz.
* pll_div2 Divide the PLL output frequency by 2 (this settings does
* not change the FVCO value)
* pll_wbwdisable 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode
* allow a faster startup time and out-of-lock time). 0 to
* enable the Wide-Bandwidth Mode.
*/
pm_pll_set_option(&AVR32_PM, 0, /* use PLL0 */
PLL_FREQ_VAL, /* pll_freq */
PLL_DIV2_VAL, /* pll_div2 */
PLL_WBWD_VAL); /* pll_wbwd */
/* Enable PLL0 */
pm_pll_enable(&AVR32_PM, 0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(&AVR32_PM);
/* Create PBA, PBB and HSB clock */
pm_cksel(&AVR32_PM, PLL_PBADIV_VAL, /* pbadiv */
PLL_PBASEL_VAL, /* pbasel */
PLL_PBBDIV_VAL, /* pbbdiv */
PLL_PBBSEL_VAL, /* pbbsel */
PLL_HSBDIV_VAL, /* hsbdiv */
PLL_HSBSEL_VAL); /* hsbsel */
/* Calculate CPU frequency */
CPUFrequency = (OSC0_VAL * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL;
CPUFrequency = (PLL_DIV2_VAL == 0) ? CPUFrequency : CPUFrequency >> 1;
if (PLL_HSBDIV_VAL > 0) {
CPUFrequency = CPUFrequency >> (PLL_HSBSEL_VAL + 1);
}
void pm_configure_usb_clock(void)
{
volatile avr32_pm_t *pm = &AVR32_PM;
#if __AVR32_UC3A3256__ || __AVR32_UC3A3128__ || __AVR32_UC3A364__ || \
__AVR32_UC3A3256S__ || __AVR32_UC3A3128S__ || __AVR32_UC3A364S__ || \
__AT32UC3A3256__ || __AT32UC3A3128__ || __AT32UC3A364__ || \
__AT32UC3A3256S__ || __AT32UC3A3128S__ || __AT32UC3A364S__
// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#else
// Set PLL1 @ 96 MHz from Osc0: 12MHz*(7+1)/1 = 96MHz.
// In order to work, we need to go above 80MHz, then divide.
pm_pll_setup(pm, 1, // pll
7, // mul
1, // div
0, // osc
16); // lockcount
pm_pll_set_option(pm, 1, // pll1
1, // Choose the range 80-180MHz.
1, // div2
0); // wbwdisable
// Enable PLL1.
pm_pll_enable(pm, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(pm);
// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc
1, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#endif
}
/*! \brief Initializes the MCU system clocks.
*/
void init_sys_clocks(void)
{
// Switch to OSC0 to speed up the booting
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Start oscillator1
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
//
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set PLL0 (fed from OSC1 = 11.2896 MHz) to 124.1856 MHz
// We use OSC1 since we need a correct master clock for the SSC module to generate
// the correct sample rate
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
1, // osc.
16); // lockcount.
// Set PLL operating range and divider (fpll = fvco/2)
// -> PLL0 output = 62.0928 MHz
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL0 and wait for the lock
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
// Set all peripheral clocks to run at master clock rate
pm_cksel(&AVR32_PM,
0, // pbadiv.
0, // pbasel.
0, // pbbdiv.
0, // pbbsel.
0, // hsbdiv.
0); // hsbsel.
// Set one waitstate for the flash
flashc_set_wait_state(1);
// Switch to PLL0 as the master clock
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
init_usb_clock();
init_codec_gclk();
}
void pm_configure_usb_clock(void)
{
#if (defined __AVR32_UC3A3256__) || (defined __AVR32_UC3A3128__) || (defined __AVR32_UC3A364__) || \
(defined __AVR32_UC3A3256S__) || (defined __AVR32_UC3A3128S__) || (defined __AVR32_UC3A364S__) || \
(defined __AT32UC3A3256__) || (defined __AT32UC3A3128__) || (defined __AT32UC3A364__) || \
(defined __AT32UC3A3256S__) || (defined __AT32UC3A3128S__) || (defined __AT32UC3A364S__)
// Setup USB GCLK.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#else
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#endif
}
void displayOnOff(void){
static uint32_t j=0;
static int32_t SEL =4;
display(15);
delay_s(100);
display(0);
delay_s(100);
if (j>6) {
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,SEL,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
SEL-=2;
if (SEL<2)
{
SEL=6;
}
j=0;
}
j++;
}
int pm_configure_clocks(pm_freq_param_t *param)
{
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
// Switch to external Oscillator 0
pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PM_FREQ_STATUS_OK;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return PM_FREQ_STATUS_FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return PM_FREQ_STATUS_FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
pm_pll_setup(&AVR32_PM
, 0 // pll
, mul // mul
, div // div
, 0 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
// PLL clock is lower than 160MHz: need to set pllopt.
, (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
, div2_en // pll_div2
, 0 // pll_wbwdisable
);
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
// Enable PLL0
pm_pll_enable(&AVR32_PM, 0);
// Wait for PLL0 locked
pm_wait_for_pll0_locked(&AVR32_PM);
if (div2_cpu)
{
b_div2_cpu = TRUE;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
if (div2_pba)
{
b_div2_pba = TRUE;
div2_pba--;
}
else
b_div2_pba = FALSE;
pm_cksel(&AVR32_PM
, b_div2_pba, div2_pba // PBA
, b_div2_cpu, div2_cpu // PBB
, b_div2_cpu, div2_cpu // HSB
);
if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
{
flashc_set_wait_state(1);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
else
{
flashc_set_wait_state(0);
#if (defined AVR32_FLASHC_210_H_INCLUDED)
if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
else
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
#endif
}
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
return PM_FREQ_STATUS_OK;
}
void board_init(void)
{
// first change to OSC0 (12MHz)
pm_enable_osc0_crystal(& AVR32_PM, FOSC0); // Enable the Osc0 in crystal mode
pm_enable_clk0(& AVR32_PM, OSC0_STARTUP); // Crystal startup time
pm_switch_to_clock(& AVR32_PM, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
pm_enable_osc1_ext_clock(& AVR32_PM); // ocs1 is external clock
pm_enable_clk1(& AVR32_PM, OSC1_STARTUP);
pm_pll_setup(&AVR32_PM
, 0 // pll
, 3 // mul
, 0 // div -> f_vfo = 16.384 MHz * 8 = 131.072 MHz
, 1 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
, 1 // pll_freq (f_vfo range 80MHz - 180 MHz)
, 1 // pll_div2 (f_pll1 = f_vfo / 2)
, 0 // pll_wbwdisable
);
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
pm_cksel(&AVR32_PM
, 1, 1 // PBA (CPU / 4) = 16.384 MHz
, 0, 0 // PBB 65.536 MHz
, 0, 0 // HSB = CPU 65.536 MHz
);
flashc_set_wait_state(1); // one wait state if CPU clock > 33 MHz
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); // switch to PLL0
// --------------------------------------
// USB clock
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
// --------------------------------------
// LCD display
gpio_enable_gpio( lcd_gpio_map, sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] ) );
int i;
for (i=0; i < (sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] )); i++)
{
gpio_configure_pin( lcd_gpio_map[i].pin, lcd_gpio_map[i].function);
}
gpio_enable_module( lcd_pwm_gpio_map, sizeof( lcd_pwm_gpio_map ) / sizeof( lcd_pwm_gpio_map[0] ) );
// Backlight
AVR32_PWM.channel[6].CMR.cpre = 3;
AVR32_PWM.channel[6].cprd = 1000;
AVR32_PWM.channel[6].cdty = 500;
AVR32_PWM.ENA.chid6 = 1;
// contrast
AVR32_PWM.channel[0].CMR.cpre = 3;
AVR32_PWM.channel[0].cprd = 1000;
AVR32_PWM.channel[0].cdty = 520;
AVR32_PWM.ENA.chid0 = 1;
// switches
gpio_enable_gpio( switch_gpio_map, sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] ) );
for (i=0; i < (sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] )); i++)
{
gpio_configure_pin( switch_gpio_map[i].pin, switch_gpio_map[i].function);
}
// USART
gpio_enable_module( usart_gpio_map, sizeof( usart_gpio_map ) / sizeof( usart_gpio_map[0] ) );
}
/**
* Initializes the MCU system clocks.
*/
static void
init_sys_clocks(void)
{
/* if we don't run on OSC0 don't switch to it since we don't know
* what kind of oscillator we have here
*/
#if OSC == 0
/* switch to OSC0 to speed up the booting */
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
#endif
#ifndef USE_PLL
return;
#endif
/* For audio, ee have to use OSC1 on to generate the correct clockrate
* for the SSC
*/
#if OSC == 1
/* start oscillator1 */
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
#endif
/* configure pll multipliers */
pm_pll_setup(&AVR32_PM,
0, /* pll */
PLL_MUL, /* mul */
1, /* div */
OSC, /* osc */
16); /* lockcount */
/* set PLL operating range and divider (fpll = fvco/2)
* this gives PLL output = 66 MHz (62.0928 MHz for EVK1105/OSC1)
*/
pm_pll_set_option(&AVR32_PM,
0, /* pll */
1, /* pll_freq */
1, /* pll_div2 */
0); /* pll_wbwdisable. */
/* start PLL0 and wait for the lock */
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
/* Set all peripheral clocks torun at master clock rate */
pm_cksel(&AVR32_PM,
0, /* pbadiv */
0, /* pbasel */
0, /* pbbdiv */
0, /* pbbsel */
0, /* hsbdiv */
0); /* hsbsel */
/* Set one waitstate for the flash */
flashc_set_wait_state(1);
/* Switch to PLL0 as the master clock */
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
}
__attribute__ ((__interrupt__)) void touch_button_isr(void){
eic_clear_interrupt_line(&AVR32_EIC, QT1081_EIC_EXTINT_INT);
// UP
if(gpio_get_pin_value(QT1081_TOUCH_SENSOR_UP))
{
//gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_UP);
//gpio_tgl_gpio_pin(LED0_GPIO);
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,vel++,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
if (vel>=6)
{
vel=6;
}
}
// DOWN
if(gpio_get_pin_value(QT1081_TOUCH_SENSOR_DOWN))
{
//gpio_tgl_gpio_pin(LED1_GPIO);
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,vel--,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
if (vel<=2)
{
vel=2;
}
}
}
__attribute__ ((__interrupt__)) void tecla_lrc_isr(void){//handler teclas left, right o center
if (gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER))
{
gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER);
}
if (gpio_get_pin_interrupt_flag (QT1081_TOUCH_SENSOR_LEFT))
{
gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_LEFT);
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
while(gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER)==0){
gpio_tgl_gpio_pin(LED3_GPIO);
delay_s(50);
}
display(0);
}
if (gpio_get_pin_interrupt_flag (QT1081_TOUCH_SENSOR_RIGHT))
{
gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_RIGHT);
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
while(gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER)==0){
displayPrimo();
delay_s(50);
}
}
if (gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_UP))
{
gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_UP);
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,2,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
while (gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER)==0)
{
displayA1();
/*for (uint32_t j =0; j<18000; j++)//300ms 12Mhz
{
delay_ms(10);
}*/
delay_s(50);
}
display(0);
}
if (gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_DOWN))
{
gpio_clear_pin_interrupt_flag(QT1081_TOUCH_SENSOR_DOWN);
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,6,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
while (gpio_get_pin_interrupt_flag(QT1081_TOUCH_SENSOR_ENTER)==0)
{
displayOnOff();
}
display(0);
}
}
/**
* @brief Start PLL @ 48Mhz to run with
*/
void Start_PLL(void)
{
volatile avr32_pm_t *pm = &AVR32_PM;
// Switch the main clock to OSC0
pm_switch_to_osc0(pm, BOARD_OSC0_HZ, BOARD_OSC0_STARTUP_US);
// For FOSC0 = 12.288 MHz:
// Setup PLL0 on OSC0, mul=15 ,no divisor, lockcount=16, ie. 12 MHz x 16 = 196.608 MHz output.
// Division by 2 (in options) yields PLL0 output as 98.304 MHz.
// The formula is here:
// if (PLLDIV > 0)
// fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
// else
// fVCO = 2*(PLLMUL+1) • fOSC;
// Lock count defines the PLL settling time (0x00 .. 0x3F.)
pm_pll_setup(
pm, // volatile avr32_pm_t *pm
0, // PLL number(0 for PLL0, 1 for PLL1)
15, // PLL MUL in the PLL formula
1, // PLL DIV in the PLL formula
0, // OSC number (0 for osc0, 1 for osc1)
16); // unsigned int lockcount
// Set PLL options to run @ 96 MHz
pm_pll_set_option(
pm, // volatile avr32_pm_t *pm
0, // PLL number(0 for PLL0, 1 for PLL1)
0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
1, // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
0); // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
// out-of-lock time). 0 to enable the Wide-Bandwidth Mode.
// Enable PLL0 and wait for it to lock.
pm_pll_enable(pm, 0);
pm_wait_for_pll0_locked(pm);
#if 0
#if defined(BOARD_OSC1_HZ)
// We need to enable the crystal by hand. We didn't need to do that for OSC0
// because the call to pm_switch_to_osc0() contains all that housekeeping.
// But here we don't want to "switch to" the crystal.
pm_enable_osc1_crystal(pm, BOARD_OSC1_HZ); // Enable the OSC1 in crystal mode
pm_enable_clk1(pm, BOARD_OSC1_STARTUP_US);
// For FOSC1 = 12.000 MHz:
// Setup PLL1 on OSC1, mul=15 ,no divisor, ie. 12 MHz x 15 = 180 MHz output.
// Division by 2 (in options) yields PLL0 output as 96.000 MHz.
// Lock count defines the PLL settling time (0x00 .. 0x3F.)
// The formula is here:
// if (PLLDIV > 0)
// fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
// else
// fVCO = 2*(PLLMUL+1) • fOSC;
pm_pll_setup(
pm, // volatile avr32_pm_t *pm
1, // PLL number(0 for PLL0, 1 for PLL1)
15, // PLL MUL in the PLL formula
1, // PLL DIV in the PLL formula
1, // OSC number (0 for osc0, 1 for osc1)
16); // unsigned int lockcount
// Set PLL options to run @ 96.000 MHz
pm_pll_set_option(
pm, // volatile avr32_pm_t *pm
1, // PLL number(0 for PLL0, 1 for PLL1)
0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
1, // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
0); // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
// out-of-lock time). 0 to enable the Wide-Bandwidth Mode.
// Enable PLL1 and wait for it to lock.
pm_pll_enable(pm, 1);
pm_wait_for_pll1_locked(pm);
#endif /* defined(BOARD_OSC1_HZ) */
#endif
// Select clocks as follows, considering that we are fed with PLL0 (98.304 MHz)
// fHSB = fMain/2, or 49.152 MHz
// fPBA = fMain/8, or 12.288 MHz
// fPBB = fMain/2, or 49.152 MHz
// ========================================
// The formula (applies to all three channels, they are the same.)
//
// if (xDIV) // Is the divisor enabled?
// fBUS = fMain / 2^(xSEL+1); // Yes
// else
// fBUS = fMain; // No
pm_cksel(
pm, // volatile avr32_pm_t *pm
true, // PBADIV: Peripheral Bus A clock divisor enable
0, // PBASEL: Peripheral Bus A divisor tap (fPBA = fMain/2, or 49.152 MHz)
true, // PBBDIV: Peripheral Bus B clock divisor enable
0, // PBBSEL: Peripheral Bus B select (fPBB = fMain/2, or 49.152 MHz)
1, // CPUDIV: CPU/HSB clock divisor enable
0); // CPUSEL: CPU/HSB clock divisor tap (fHSB = fMain/2, or 49.152 MHz)
// One wait state at 48 MHz (required at fHSB > 33 MHz)
flashc_set_wait_state(1);
// Select the PLL0 as the clock source.
pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0);
#if 0
#if defined(BOARD_OSC1_HZ)
// Timers, communication modules, and other modules connected to external circuitry may require
// specific clock frequencies to operate correctly. The Power Manager contains an implementation
// defined number of generic clocks that can provide a wide range of accurate clock frequencies.
// Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
// can optionally be divided by any even integer up to 512. Each clock can be independently
// enabled and disabled, and is also automatically disabled along with peripheral clocks by the
// Sleep Controller.
// Setup generic clock number 0 on PLL, with OSC0/PLL0, no divisor.
// A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
// either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
// The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
// resulting in the output frequency:
//
// fGCLK = fSRC / (2*(DIV+1))
//
// In this particular case we enable the generic clock to the USB module. Since the PLL1 is
// producing 96.000 MHz we want to divide it by 2 to whittle it down to 48.000 +/- 0.25%.
// The 48 MHz is the only clock that the USB module can use.
//
pm_gc_setup(
pm, // volatile avr32_pm_t *pm
AVR32_PM_GCLK_USBB, // Generic clock number
1, // Use Osc (=0) or PLL (=1)
1, // Select Osc0/PLL0 or Osc1/PLL1
1, // DIVEN: Generic clock divisor enable
0); // DIV: Generic clock divisor (divide by 2)
// Enable Generic clock 4 */
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#endif
#endif
#if 0 // Enable only for debugging, or if you really need to output the generic clock...
pm_gc_setup(
pm, // volatile avr32_pm_t *pm
AVR32_PM_GCLK_GCLK0, // Generic clock number
1, // Use Osc (=0) or PLL (=1)
0, // Select Osc0/PLL0 or Osc1/PLL1
0, // DIVEN: Generic clock divisor enable
1); // DIV: Generic clock divisor (divide by 0)
// Enable Generic clock 0 */
pm_gc_enable(pm, AVR32_PM_GCLK_GCLK0);
/* Output the clock AVR32_PM_GCLK_GCLK0 to a GPIO (PB19) */
gpio_enable_module_pin(AVR32_PM_GCLK_0_1_PIN, AVR32_PM_GCLK_0_1_FUNCTION);
#endif
}
/* \brief Start PLL0, switch main clock to PLL0 output.
*
*
*/
static void local_start_highfreq_clock(void)
{
#if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
scif_dfll_openloop_conf_t dfllconfig = {EXAMPLE_DFLL_FINE_FDFLL96, EXAMPLE_DFLL_COARSE_FDFLL96};
// Configure and start the DFLL0 in open loop mode to generate a frequency of 96MHz.
scif_dfll0_openloop_start(&dfllconfig);
// Since our target is to set the CPU&HSB frequency domains to 48MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
// Set the CPU clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
// Set the PBA clock domain to 24MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_DFLL0);
#elif BOARD == UC3C_EK || BOARD == STK600_RCUC3D
scif_pll_opt_t opt;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 5; // MUL=6 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
#if UC3D
flashcdw_set_wait_state(1);
#else
flashc_set_wait_state(1);
#endif
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else
volatile avr32_pm_t* pm = &AVR32_PM;
/* \note All calculations here suppose that the Osc0 frequency is 12MHz. */
pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP); // Switch main clock to Osc0.
/* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 12Mhzx8 = 96MHz output */
/*void pm_pll_setup(volatile avr32_pm_t* pm,
unsigned int pll,
unsigned int mul,
unsigned int div,
unsigned int osc,
unsigned int lockcount) {
*/
pm_pll_setup(pm,
0, // use PLL0
7, // MUL=7 in the formula
1, // DIV=1 in the formula
0, // Sel Osc0/PLL0 or Osc1/PLL1
16); // lockcount in main clock for the PLL wait lock
/*
This function will set a PLL option.
*pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number 0
pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
/* PLL output VCO frequency is 96MHz. We divide it by 2 with the pll_div2=1. This enable to get later main clock to 48MHz */
pm_pll_set_option(pm, 0, 1, 1, 0);
/* Enable PLL0 */
/*
void pm_pll_enable(volatile avr32_pm_t* pm,
unsigned int pll) {
*/
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_cksel(pm, 1, 0, 0, 0, 0, 0);
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
flashc_set_wait_state(1);
pm_switch_to_clock(pm, AVR32_PM_MCSEL_PLL0); /* Switch main clock to 48MHz */
#endif
}
static void clockfrequencies_configure(void)
{
#if UC3L
static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, false };
static pcl_freq_param_t pcl_dfll_freq_param =
{
.main_clk_src = PCL_MC_DFLL0,
.cpu_f = EXAMPLE_MCUCLK_HZ,
.pba_f = EXAMPLE_MCUCLK_HZ,
.pbb_f = EXAMPLE_MCUCLK_HZ,
.dfll_f = EXAMPLE_FDFLL_HZ,
.pextra_params = &gc_dfllif_ref_opt
};
// Implementation for UC3L
// Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
// to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
// main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
// Note: since it is dynamically computing the appropriate field values of the
// configuration registers from the parameters structure, this function is not
// optimal in terms of code size. For a code size optimal solution, it is better
// to create a new function from pcl_configure_clocks_dfll0() and modify it
// to use preprocessor computation from pre-defined target frequencies.
#elif UC3C
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
scif_pll_opt_t opt;
// Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 7; // MUL=7 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
// Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC
/* Set the main clock source as being PLL0. */
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#elif UC3D
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
scif_pll_opt_t opt;
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (12Mhzx11)/2 = 66MHz output
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 10; // MUL=10 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; // pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
// Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 33MHz
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
/* Set the main clock source as being PLL0. */
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else // UC3A and UC3B series
// Switch the main clock source to Osc0.
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
0, // osc.
16); // lockcount.
// PLL output VCO frequency is 132MHz.
// We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz.
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// Enable the PLL.
pm_pll_enable(&AVR32_PM, 0);
// Wait until the PLL output is stable.
pm_wait_for_pll0_locked(&AVR32_PM);
// Configure each clock domain to use the main clock divided by 2
// => fCPU = fPBA = fPBB = 33MHz.
pm_cksel(&AVR32_PM,
1, // pbadiv.
0, // pbasel.
1, // pbbdiv.
0, // pbbsel.
1, // hsbdiv=cpudiv
0); // hsbsel=cpusel
// Switch the main clock source to PLL0.
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
#endif
}
void displayA1(void){
static uint32_t i=0;
static uint32_t j=0;
static uint32_t SEL =4;
uint32_t arr[]={0,6,15,6};
display(arr[i]);
i++;
if (i>3)
{
i=0;
if (j>6)
{/*
pm_cksel(&AVR32_PM,//CAMBIA FREQ DEL CPU
0,//PBA DIV
0,//PBA SEL
0,//PBB DIV
0,//PBB SEL
1,//CPU DIV
SEL);//CPU SEL 2^(SEL+1)
SEL++;
if (SEL>2)
{
SEL=0;
}*/
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,SEL,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
SEL+=2;
if (SEL>=8)
{
SEL=2;
}
j=0;
}
j++;
}
}
void Actividad1(void){
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); //osc0 a 12Mhz
while (1)
{
if (debounce2(QT1081_TOUCH_SENSOR_LEFT))
{
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
while(gpio_get_pin_value(QT1081_TOUCH_SENSOR_ENTER)==0)
{
gpio_tgl_gpio_pin(LED3_GPIO);
delay_s(50);
}
display(0);
}
if (debounce2(QT1081_TOUCH_SENSOR_RIGHT))
{
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
while (gpio_get_pin_value(QT1081_TOUCH_SENSOR_ENTER)==0)
{
displayPrimo();
delay_s(50);
}
}
if (debounce2(QT1081_TOUCH_SENSOR_UP))
{
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,2,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
while (gpio_get_pin_value(QT1081_TOUCH_SENSOR_ENTER)==0)
{
displayA1();
delay_s(50);
}
display(0);
}
if (debounce2(QT1081_TOUCH_SENSOR_DOWN))
{
pm_switch_to_clock(&AVR32_PM,0); //cambia al RC
pm_pll_disable(&AVR32_PM,0); // deshabilita el el PLL 0
pm_pll_setup(&AVR32_PM,0,6,1,0,16); // lockcount in main clock for the PLL wait lock
//_______________________________________________________________________________
// Establece la frecuencia de salida del PLL
pm_pll_set_option(&AVR32_PM,0,1,0,0);//1 Star-up faster, Start-up normal
//_______________________________________________________________________________
//Habilita el PLL 0
pm_pll_enable(&AVR32_PM,0);
//_______________________________________________________________________________
//Espera a que se establesca el PLL
pm_wait_for_pll0_locked(&AVR32_PM) ;
//_______________________________________________________________________________
// Set one wait-state (WS) for flash controller
flashc_set_wait_state(1);
//habilita la salida del PLL0 con 2 y el OSC0 con 1
pm_switch_to_clock(&AVR32_PM, 2);
while (gpio_get_pin_value(QT1081_TOUCH_SENSOR_ENTER)==0)
{
displayOnOff();
}
display(0);
}
}
}
//!
//! \fn main
//! \brief start the software here
//! 1) Initialize the microcontroller and the shared hardware resources
//! of the board.
//! 2) Launch the IP modules.
//! 3) Start FreeRTOS.
//! \return 42, which should never occur.
//! \note
//!
int main( void )
{
volatile avr32_pm_t* pm = &AVR32_PM;
/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
/* Switch to external oscillator 0 */
pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
Extra div by 2 => 96MHz */
pm_pll_setup(pm, /* volatile avr32_pm_t* pm */
0, /* unsigned int pll */
15, /* unsigned int mul */
1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
0, /* unsigned int osc */
16); /* unsigned int lockcount */
pm_pll_set_option( pm, 0, // pll0
0, // Choose the range 160-240MHz.
1, // div2
0 ); // wbwdisable
/* Enable PLL0 */
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
pm_gc_setup(pm,
0,
1, /* Use Osc (=0) or PLL (=1) */
0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
0,
1);
/* Enable Generic clock 0*/
pm_gc_enable(pm, 0);
/* switch to clock */
pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
flashc_set_wait_state( 1 );
pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
/* Setup the LED's for output. */
vParTestInitialise();
/* Start the flash tasks just to provide visual feedback that the demo is
executing. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
/* 2) Start ethernet task. */
vStartEthernetTask( mainETH_TASK_PRIORITY );
/* 3) Start FreeRTOS. */
vTaskStartScheduler();
/* Will only reach here if there was insufficient memory to create the idle task. */
return 0;
}