int main(void)
{
// Disable watchdog timer
wdt_disable(WDT);
// Enable peripheral clock to be able to read button state
pmc_enable_periph_clk(BUTTONS_PIO_ID);
while (!pmc_is_periph_clk_enabled(BUTTONS_PIO_ID));
// Configure pins
pio_set_output(LEDS_PIO, ALL_LEDS, 1, false, false);
pio_set_input(BUTTONS_PIO, ALL_BUTTONS, PIO_PULLUP);
while (true)
{
pio_set(LEDS_PIO, LED_ORANGE);
pio_clear(LEDS_PIO, LED_GREEN);
while (pio_get(BUTTONS_PIO, PIO_INPUT, BUTTON1));
pio_clear(LEDS_PIO, LED_ORANGE);
pio_set(LEDS_PIO, LED_GREEN);
while (pio_get(BUTTONS_PIO, PIO_INPUT, BUTTON2));
}
return 0;
}
/**
* Configure the MCI SDCBUS in the MCI_SDCR register. Only two modes available
*
* \param pMci Pointer to the low level MCI driver.
* \param busWidth MCI bus width mode. 00: 1-bit, 10: 4-bit, 11: 8-bit.
*/
uint32_t MCI_SetBusWidth(Mcid*pMci, uint32_t busWidth)
{
Hsmci *pMciHw = pMci->pMciHw;
uint32_t mciSdcr;
uint32_t mciDis;
assert(pMci);
assert(pMci->pMciHw);
if( (busWidth != HSMCI_SDCR_SDCBUS_1) && (busWidth != HSMCI_SDCR_SDCBUS_4) && (busWidth != HSMCI_SDCR_SDCBUS_8) )
{
return (uint32_t)-1;
}
busWidth &= HSMCI_SDCR_SDCBUS_Msk ;
pmc_enable_periph_clk(pMci->mciId);
mciDis = pmc_is_periph_clk_enabled(pMci->mciId);
mciSdcr = (pMciHw->HSMCI_SDCR & ~(uint32_t)(HSMCI_SDCR_SDCBUS_Msk));
pMciHw->HSMCI_SDCR = mciSdcr | busWidth;
if (mciDis)
{
// pmc_disable_periph_clk(pMci->mciId);
}
return 0;
}
/**
* Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is
* MCK/2 and corresponds to CLKDIV = 0
* \param pMci Pointer to the low level MCI driver.
* \param mciSpeed MCI clock speed in Hz, 0 will not change current speed.
* \param mck MCK to generate MCI Clock, in Hz
* \return The actual speed used, 0 for fail.
*/
uint32_t MCI_SetSpeed( Mcid* pMci, uint32_t mciSpeed, uint32_t mck )
{
Hsmci *pMciHw = pMci->pMciHw;
uint32_t mciMr;
uint32_t clkdiv;
uint32_t mciDis;
assert(pMci);
assert(pMciHw);
pmc_enable_periph_clk(pMci->mciId);
mciDis = pmc_is_periph_clk_enabled(pMci->mciId);
mciMr = pMciHw->HSMCI_MR & (~(uint32_t)HSMCI_MR_CLKDIV_Msk);
/* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
* divided by (2*(CLKDIV+1))
* mciSpeed = MCK / (2*(CLKDIV+1)) */
if (mciSpeed > 0)
{
clkdiv = (mck / 2 / mciSpeed);
/* Speed should not bigger than expired one */
if (mciSpeed < mck/2/clkdiv)
{
clkdiv ++;
}
if ( clkdiv > 0 )
{
clkdiv -= 1;
}
assert( (clkdiv & 0xFFFFFF00) == 0 ) ; /* "mciSpeed too small" */
}
else
{
clkdiv = 0 ;
}
/* Actual MCI speed */
mciSpeed = mck / 2 / (clkdiv + 1);
/* Modify MR */
pMciHw->HSMCI_MR = mciMr | clkdiv;
if ( mciDis )
{
// pmc_disable_periph_clk( pMci->mciId ) ;
}
return (mciSpeed);
}
OSStatus platform_uart_deinit( platform_uart_driver_t* driver )
{
OSStatus err = kNoErr;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ), exit, err = kParamErr);
usart_disable_interrupt( driver->peripheral->port, 0xffffffff );
NVIC_DisableIRQ( platform_flexcom_irq_numbers[driver->peripheral->uart_id] );
pdc_disable_transfer( usart_get_pdc_base( driver->peripheral->port ), PERIPH_PTCR_TXTDIS | PERIPH_PTCR_RXTDIS );
usart_disable_tx( driver->peripheral->port );
usart_disable_rx( driver->peripheral->port );
if( pmc_is_periph_clk_enabled( driver->peripheral->peripheral_id ) == 1 ) {
flexcom_disable( driver->peripheral->flexcom_base );
}
platform_gpio_deinit( driver->peripheral->tx_pin );
platform_gpio_deinit( driver->peripheral->rx_pin );
if ( driver->peripheral->cts_pin != NULL )
{
platform_gpio_deinit( driver->peripheral->cts_pin );
}
if ( driver->peripheral->rts_pin != NULL )
{
platform_gpio_deinit( driver->peripheral->rts_pin );
}
#ifndef NO_MICO_RTOS
mico_rtos_deinit_semaphore(&driver->rx_complete);
mico_rtos_deinit_semaphore(&driver->tx_complete);
#endif
driver->peripheral = NULL;
memset( driver, 0, sizeof(platform_uart_driver_t) );
exit:
platform_mcu_powersave_enable();
return err;
}
/**
* Configure the MCI_CFG to enable the HS mode
* \param pMci Pointer to the low level MCI driver.
* \param hsEnable 1 to enable, 0 to disable HS mode.
*/
uint8_t MCI_EnableHsMode(Mcid* pMci, uint8_t hsEnable)
{
Hsmci *pMciHw = pMci->pMciHw;
uint32_t cfgr;
uint32_t mciDis;
uint8_t rc = 0;
assert(pMci);
assert(pMci->pMciHw);
pmc_enable_periph_clk(pMci->mciId);
mciDis = pmc_is_periph_clk_enabled(pMci->mciId);
cfgr = pMciHw->HSMCI_CFG;
if (hsEnable == 1)
{
cfgr |= HSMCI_CFG_HSMODE;
}
else
{
if (hsEnable == 0)
{
cfgr &= ~(uint32_t)HSMCI_CFG_HSMODE;
}
else
{
rc = ((cfgr & HSMCI_CFG_HSMODE) != 0);
}
}
pMciHw->HSMCI_CFG = cfgr;
if (mciDis)
{
// pmc_disable_periph_clk(pMci->mciId);
}
return rc;
}
/**
* Reset MCI HW interface and disable it.
* \param keepSettings Keep old register settings, including
* _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG.
*/
void MCI_Reset(Mcid *pMci, uint8_t keepSettings)
{
Hsmci *pMciHw = pMci->pMciHw;
uint32_t mciDis;
assert(pMci);
assert(pMci->pMciHw);
pmc_enable_periph_clk(pMci->mciId);
mciDis = pmc_is_periph_clk_enabled( pMci->mciId );
if (keepSettings)
{
uint32_t mr, sdcr, dtor, cstor;
uint32_t cfg;
mr = pMciHw->HSMCI_MR;
sdcr = pMciHw->HSMCI_SDCR;
dtor = pMciHw->HSMCI_DTOR;
cstor = pMciHw->HSMCI_CSTOR;
cfg = pMciHw->HSMCI_CFG;
MCI_RESET(pMciHw);
MCI_Disable(pMciHw);
pMciHw->HSMCI_MR = mr;
pMciHw->HSMCI_SDCR = sdcr;
pMciHw->HSMCI_DTOR = dtor;
pMciHw->HSMCI_CSTOR = cstor;
pMciHw->HSMCI_CFG = cfg;
}
else
{
MCI_RESET(pMciHw);
MCI_Disable(pMciHw);
}
if ( mciDis )
{
// pmc_disable_periph_clk( pMci->mciId ) ;
}
}
OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
{
pdc_packet_t pdc_uart_packet, pdc_uart_tx_packet;
OSStatus err = kNoErr;
sam_usart_opt_t settings;
bool hardware_shaking = false;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
require_action_quiet( (optional_ring_buffer->buffer != NULL ) && (optional_ring_buffer->size != 0), exit, err = kUnsupportedErr);
driver->rx_size = 0;
driver->tx_size = 0;
driver->rx_ring_buffer = optional_ring_buffer;
driver->last_transmit_result = kNoErr;
driver->last_receive_result = kNoErr;
driver->peripheral = (platform_uart_t*)peripheral;
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore( &driver->tx_complete, 1 );
mico_rtos_init_semaphore( &driver->rx_complete, 1 );
mico_rtos_init_semaphore( &driver->sem_wakeup, 1 );
mico_rtos_init_mutex ( &driver->tx_mutex );
#else
driver->tx_complete = false;
driver->rx_complete = false;
#endif
/* Set Tx and Rx pin mode to UART peripheral */
platform_gpio_peripheral_pin_init( peripheral->tx_pin, ( peripheral->tx_pin_mux_mode | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( peripheral->rx_pin, ( peripheral->rx_pin_mux_mode | IOPORT_MODE_PULLUP ) );
/* Init CTS and RTS pins (if available) */
if ( peripheral->cts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) )
{
hardware_shaking = true;
platform_gpio_peripheral_pin_init( peripheral->cts_pin, ( peripheral->cts_pin_mux_mode | IOPORT_MODE_PULLUP ) );
}
if ( peripheral->rts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) )
{
hardware_shaking = true;
platform_gpio_peripheral_pin_init( peripheral->rts_pin, ( peripheral->rts_pin_mux_mode | IOPORT_MODE_PULLUP ) );
}
/* Enable the clock. */
if( pmc_is_periph_clk_enabled( peripheral->peripheral_id ) == 0 ) {
flexcom_enable( peripheral->flexcom_base );
}
flexcom_set_opmode( peripheral->flexcom_base, FLEXCOM_USART );
/* Enable the receiver and transmitter. */
usart_reset_tx( peripheral->port );
usart_reset_rx( peripheral->port );
/* Disable all the interrupts. */
usart_disable_interrupt( peripheral->port, 0xffffffff );
switch ( config->parity ) {
case NO_PARITY:
settings.parity_type = US_MR_PAR_NO;
break;
case EVEN_PARITY:
settings.parity_type = US_MR_PAR_EVEN;
break;
case ODD_PARITY:
settings.parity_type = US_MR_PAR_ODD;
break;
default:
err = kParamErr;
goto exit;
}
switch ( config->data_width) {
case DATA_WIDTH_5BIT:
settings.char_length = US_MR_CHRL_5_BIT;
break;
case DATA_WIDTH_6BIT:
settings.char_length = US_MR_CHRL_6_BIT;
break;
case DATA_WIDTH_7BIT:
settings.char_length = US_MR_CHRL_7_BIT;
break;
case DATA_WIDTH_8BIT:
settings.char_length = US_MR_CHRL_8_BIT;
break;
case DATA_WIDTH_9BIT:
settings.char_length = US_MR_MODE9;
break;
default:
err = kParamErr;
goto exit;
}
settings.baudrate = config->baud_rate;
settings.stop_bits = ( config->stop_bits == STOP_BITS_1 ) ? US_MR_NBSTOP_1_BIT : US_MR_NBSTOP_2_BIT;
settings.channel_mode= US_MR_CHMODE_NORMAL;
/* Configure USART in serial mode. */
if (!hardware_shaking) {
usart_init_rs232( peripheral->port, &settings, sysclk_get_peripheral_hz());
} else {
usart_init_hw_handshaking( peripheral->port, &settings, sysclk_get_peripheral_hz());
}
/* Enable uart interrupt */
NVIC_SetPriority( platform_flexcom_irq_numbers[peripheral->uart_id], 0x06 );
NVIC_EnableIRQ( platform_flexcom_irq_numbers[peripheral->uart_id] );
/* Enable PDC transmit */
pdc_enable_transfer( usart_get_pdc_base( peripheral->port ), PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN );
pdc_disable_transfer( usart_get_pdc_base( driver->peripheral->port ), PERIPH_PTCR_TXTDIS );
pdc_uart_packet.ul_addr = (uint32_t)driver->rx_ring_buffer->buffer;
pdc_uart_packet.ul_size = (uint32_t)driver->rx_ring_buffer->size;
pdc_rx_init( usart_get_pdc_base( peripheral->port ), &pdc_uart_packet, &pdc_uart_packet );
pdc_uart_tx_packet.ul_addr = (uint32_t)0;
pdc_uart_tx_packet.ul_size = (uint32_t)1;
pdc_tx_init( usart_get_pdc_base( driver->peripheral->port ), &pdc_uart_tx_packet, NULL );
usart_enable_interrupt( peripheral->port, US_IER_ENDRX | US_IER_RXBUFF | US_IER_RXRDY | US_IER_ENDTX );
/* Enable the receiver and transmitter. */
usart_enable_tx( peripheral->port );
usart_enable_rx( peripheral->port );
exit:
platform_mcu_powersave_enable( );
return err;
}
